Senior Power Analysis and Optimization Engineer - United States
Originally posted 16 October 2026 by the employer. Relisted by the employer on 17 October 2026.
About the role
Analyze full-chip and unit-level energy consumption and develop AI- and LLM-driven modeling, analysis, and optimization flows for GPUs and Tegra SoCs.
What you'll do
- Analyze full-chip and unit-level power using internal and industry-standard RTL and gate-level power tools, translating data into design and architectural improvements.
- Develop and productionize power-aware models and flows, including ML/RL-based techniques for anomaly detection, dynamic power management, and design-space exploration.
- Design and train custom LLMs on design data, power reports, and bug histories to interpret power data, propose root causes, and recommend architectural and micro-architectural optimizations.
- Perform comparative power analysis across workloads, products, and design options to identify trends, anomalies, and optimization opportunities.
- Partner with Architects, Performance, Software, ASIC Design, and Physical Design teams to interpret power data, root-cause power bugs, and drive fixes.
- Prototype and evaluate architectural features in Verilog, and automate analysis pipelines using Python, Perl, or C++.
What you'll need
- MS and 5+ years of experience, or PhD and 3+ years of experience in EE, CE, CS, or a related field (or equivalent experience).
- Strong understanding of energy consumption, power estimation, data movement, and low-power design.
- Familiarity with Verilog and ASIC design principles, and hands-on experience with tools such as PowerArtist, PrimePower/PrimePower RTL, RTL Architect, or similar.
- Coding and automation skills in Python, Perl, and C++.
- Experience or strong interest in machine learning, reinforcement learning, and data analytics applied to EDA, architecture, or system-level optimization.
- Interest or experience in building and using LLMs or foundation models as engineering copilots for EDA, power, or architecture workflows.
Skills: power analysis, power optimization, AI/ML for power, RTL power tools, gate-level power tools, Verilog
More semiconductor jobs: Power electronics jobs
This role has been open 227 days — well above the 96-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
69
|
Median days open
96 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (69 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 69 |
| Open roles in the wider Analog & Mixed-Signal family | 26 | 1550 · 107 employers |
| Median days open | 188 d | 96 d (+92 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: power analysis, power optimization, AI/ML for power, RTL power tools, gate-level power tools, Verilog
Who's hiring in this category
- Renesas Electronics · 14 open roles · median 102 d
- Qualcomm · 8 open roles · median 77 d
- Infineon Technologies · 7 open roles · median 71 d
- Analog Devices · 5 open roles · median 97 d
- Monolithic Power Systems · 5 open roles · median 223 d
- AMD · 4 open roles · median 88 d
How we counted: 69 open Power Electronics (Power Management) roles from 22 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.