Senior Physical Design Engineer - San Jose, California, United States
$138,000 - $206,000 USD yearly
Originally posted 19 August 2026 by the employer.
Design physical implementations for memory-centric computing IP and SoC partitions.
About the role
This role involves owning the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, focusing on solving complex system-level challenges posed by AI/ML workloads.
What you'll do
- Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing.
- Drive block- and full-chip-level PPA convergence and timing closure across multiple process corners and operating modes.
- Develop floorplans, power delivery networks, and macro placement strategies for memory controllers, NoC, and high-bandwidth interconnect subsystems.
- Perform static timing analysis (STA), constraint development, and signoff, resolving setup/hold timing, IR-drop, electromigration, and signal integrity issues.
- Execute physical verification and signoff (DRC, LVS, antenna, and reliability checks) in collaboration with foundry and standard-cell/memory library teams on advanced process nodes.
- Develop and automate physical implementation flows and methodologies using Tcl/Python scripting.
What you'll need
- Bachelor's with 5+ years, or Master's with 3+ years, or PhD's with 0+ years of industry experience.
- Strong background in digital physical design and VLSI implementation.
- 5+ years of experience in physical design implementation — synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure — for complex ASIC/SoC designs.
- Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC.
- Experience with static timing analysis and constraint (SDC) development, low-power design (UPF/CPF), and power, IR-drop, and electromigration analysis.
- Experience with physical verification (DRC, LVS, antenna) and tapeout on advanced FinFET process nodes.
- Experience implementing memory controllers, NoC, or high-speed interconnect IP and full-chip SoC integration.
- Proficiency in scripting (Tcl, Python, or Perl) for physical design flow automation.
- Experience in AI/ML workloads.
Skills: physical implementation, floorplanning, CTS, timing closure, DRC LVS
This role has been open 58 days — below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (664 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 664 |
| Open roles in the wider Physical Implementation family | 3 | 1449 · 110 employers |
| Median days open | 58 d | 60 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical implementation, floorplanning, CTS, timing closure, DRC LVS
Who's hiring in this category
- Qualcomm · 122 open roles · median 44 d
- AMD · 63 open roles · median 22 d
- NVIDIA · 40 open roles · median 70 d
- Synopsys · 37 open roles · median 30 d
- Intel Corporation · 34 open roles · median 9 d
- Broadcom · 32 open roles · median 95 d
How we counted: 664 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.