Senior Physical Design Engineer - San Jose, California, United States

Originally posted 8 August 2026 by the employer.

About the role

What you'll do

• Perform physical design implementation of custom IP and SoC designs from RTL through GDSII.
• Execute all aspects of the physical design flow, including synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), power and clock distribution, reliability analysis, and power/noise analysis.
• Perform physical verification and design signoff, including formal equivalence checking, static timing verification, reliability verification, power integrity analysis, layout verification, electrical rule checking (ERC), and structural design checking.
• Analyze implementation and signoff results, identify violations, and develop solutions.
• Optimize physical designs to improve power, performance, frequency, and area (PPA).
• Participate in the development and continuous improvement of physical design methodologies, design flows, and automation.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• 6+ years of hands-on experience with digital ASIC or SoC physical design implementation.
• 6+ years of experience performing RTL-to-GDSII physical design flows.
• 6+ years of experience with synthesis, floorplanning, place and route, and clock tree synthesis (CTS).
• 6+ years of experience performing static timing analysis (STA) and timing closure.
• 4+ years of experience with physical verification, including DRC, LVS, ERC, and signoff methodologies.
• 4+ years of experience using industry-standard physical design EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, or equivalent.
• 3+ years of experience optimizing designs for power, performance, and area (PPA).
• 2+ years of experience supporting designs with multiple voltage or power domains.

Nice to have

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience with advanced semiconductor process nodes (7nm, 5nm, 3nm, or similar).
• Experience implementing DFT-aware physical design flows and scan chain optimization.
• Experience with physical design automation, scripting, and methodology development using Python, Tcl, Perl, or Shell.
• Experience working on large-scale SoC or FPGA architectures.
• Familiarity with power integrity, IR drop, electromigration (EM), and signal integrity analysis.
• Experience collaborating across architecture, RTL, timing, DFT, verification, and CAD teams in a high-volume product development environment.

Skills: RTL through GDSII, synthesis, floorplanning, place and route, static timing analysis