Originally posted 6 August 2026 by the employer.
About the role
Mueon is hiring a Senior Physical Design Engineer (RTL-to-GDS) to lead digital implementation flows for AI computing platforms. The role owns physical implementation strategy for complex IP blocks and SoC subsystems from RTL handoff through tapeout.
What you'll do
- Own end-to-end RTL-to-GDS implementation for complex IP blocks and SoC subsystems, including synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff.
- Drive timing closure across multiple operating modes and process corners, resolving setup, hold, signal integrity, and clocking challenges.
- Lead power optimization and signoff, including dynamic power, leakage, IR drop, electromigration, and low-power implementation methodologies.
- Collaborate with architecture and RTL teams to guide floorplanning, power planning, and implementation decisions early in the design cycle.
- Drive physical verification closure, engineering change orders (ECOs), and tapeout readiness through final signoff.
- Develop automation, scripts, and methodologies using Tcl, Python, or Perl to improve implementation quality and engineering productivity.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.
- 7+ years of experience leading RTL-to-GDS implementation for ASIC or SoC designs through successful tapeout.
- Extensive experience with synthesis, floorplanning, placement, clock tree synthesis, routing, and physical implementation using industry-standard EDA tools.
- Strong expertise with static timing analysis, including MCMM timing closure, signal integrity analysis, and OCV/AOCV/POCV methodologies.
- Experience with physical verification, engineering change order (ECO) implementation, and tapeout signoff.
- Strong understanding of power optimization, IR drop, electromigration, and low-power implementation techniques.
- Experience developing automation using Tcl, Python, Perl, or similar scripting languages.
Nice to have
- Experience with advanced semiconductor process technologies (10 nm and below).
- Experience implementing large AI accelerators, CPUs, GPUs, networking ASICs, or high-performance SoCs.
- Experience with memory subsystems, embedded SRAM, or high-bandwidth memory integration.
- Experience with formal equivalence checking, reliability analysis, and advanced signoff methodologies.
- Ownership of hierarchical implementation, multi-die physical planning, die-to-die interface implementation, and package-aware floorplanning.
- Experience with multi-die, chiplet-based, or 2.5D/3D integrated designs.
More semiconductor jobs: RTL design jobs · Hillsboro jobs
First seen in our index 0 days ago, well below the 65-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1098
|
Median days since first seen
65 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Mueon | All employers we track in this specialty (1098 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1098 |
| Open roles in the wider Digital Design & Verification family | 8 | 3506 · 120 employers |
| Median days since first seen | 0 d | 65 d (+65 d vs this employer) |
| Median salary (USD postings) | n/a | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 74 d
- AMD · 92 open roles · median 55 d
- Synopsys · 89 open roles · median 54 d
- NVIDIA · 48 open roles · median 67 d
- NXP Semiconductors · 45 open roles · median 110 d
- Analog Devices · 40 open roles · median 57 d
How we counted: 1098 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.