Senior Physical Design Engineer - CA, Santa Clara, United States
Originally posted 22 September 2026 by the employer.
About the role
This role involves leading and contributing to advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff, and design optimization across block, subsystem, and chip-level designs.
What you'll do
- Lead physical design activities across block, subsystem, and chip-level implementations.
- Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
- Develop and enhance physical design methodologies, design flows, and automation solutions.
- Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
- Define and execute engineering change (ECO) strategies throughout implementation and signoff.
- Support formal verification, physical verification, and tapeout preparation activities.
What you'll need
- Experience with ASIC physical design, implementation, and timing closure.
- Experience working across block, subsystem, and chip-level design environments.
- Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
- Experience with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus.
- Experience with timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal.
- Advanced-node semiconductor design experience.
- Strong scripting and automation skills using TCL, Python, Perl, Pandas, or similar technologies.
Nice to have
- Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows.
- Experience with data analysis, database technologies, and design-quality metrics.
Skills: physical design, timing closure, signoff, advanced-node, Synopsys ICC2, PrimeTime
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
633
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (633 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 633 |
| Open roles in the wider Physical Implementation family | 62 | 1414 · 108 employers |
| Median days open | 38 d | 61 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design, timing closure, signoff, advanced-node, Synopsys ICC2, PrimeTime
Who's hiring in this category
- Qualcomm · 122 open roles · median 37 d
- Broadcom · 39 open roles · median 72 d
- NVIDIA · 38 open roles · median 47 d
- AMD (this employer) · 36 open roles · median 38 d
- Synopsys · 27 open roles · median 61 d
- Renesas Electronics · 25 open roles · median 49 d
How we counted: 633 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.