$121,800 - $182,600 USD yearly
Originally posted September 10, 2026 by the employer.
About the role
As a Senior Performance Engineer, you will define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development.
What you'll do
- Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance and low-power products.
- Create architectures, circuit specifications, logic designs, and system simulations based on system-level requirements.
- Collaborate across software architecture and hardware architecture teams to develop and execute implementation strategies meeting system requirements.
- Evaluate process flow across high-level design, synthesis, place and route, timing, power use, and verification, or custom circuit design/layout flows.
- Utilize tools and applications such as RTL to GDS Flow and Virtuoso to execute architecture and design of blocks, SoCs, or IC packages.
- Write detailed technical documentation for EDA, IP, and ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related work experience (or Master's degree with 1+ year, or PhD).
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 3 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
Skills: ASIC design, architecture, RTL to GDS Flow, synthesis, place and route
More semiconductor jobs: Qualcomm jobs · SoC design jobs · Austin jobs
First seen in our index 64 days ago, below the 72-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
520
|
Median days since first seen
72 d
|
Category median salary (all employers)
$228k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (520 roles · 70 employers) |
|---|---|---|
| Open roles in this specialty | 94 | 520 |
| Open roles in the wider Digital Design & Verification family | 454 | 3639 · 122 employers |
| Median days since first seen | 66 d | 72 d (+6 d vs this employer) |
| Median salary (USD postings) | n/a | $228k |
Skills observed across this category: ASIC design, architecture, RTL to GDS Flow, synthesis, place and route
Who's hiring in this category
- Qualcomm (this employer) · 92 open roles · median 73 d
- NVIDIA · 69 open roles · median 86 d
- AMD · 41 open roles · median 72 d
- Apple · 40 open roles · median 14 d
- Arm Holdings · 28 open roles · median 17 d
- Micron Technology · 21 open roles · median 113 d
How we counted: 520 open SoC/Chip Architecture (SOC Architecture) roles from 70 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.