Senior PCB Library Engineer - CA, Santa Clara, United States
Originally posted 9 July 2026 by the employer.
Develop, validate, and release PCB library assets using Cadence Allegro across Data Center, AI, and Networking platforms.
About the role
NVIDIA is seeking a Senior PCB Library Engineer to own the development, validation, and release of PCB library assets supporting computing platforms across Data Center, AI, Networking, Automotive, and Graphics businesses. You will serve as a technical expert for PCB component implementation, footprint architecture, padstack development, and library quality.
What you'll do
- Develop, validate, and release PCB footprints, padstacks, schematic symbols, panel definitions, and mechanical library content using Cadence Allegro and related design tools. - Review component package drawings, supplier specifications, and engineering requirements to create robust, manufacturable library data. - Partner with PCB Layout, Mechanical Engineering, Component Engineering, Manufacturing, SI/PI, and Operations teams to resolve technical issues and enforce DFM, DFA, and DFT principles. - Establish and maintain library standards, development procedures, and quality control methodologies across the PCB design ecosystem. - Support advanced technologies including HDI, fine pitch devices, via-in-pad, high-speed interconnects, and advanced package integration. - Lead root cause investigations for component implementation issues and drive workflow automation and library scalability initiatives.
What you'll need
- BS degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, or a related field (or equivalent experience). - 6+ years of experience in PCB library development, PCB layout, component engineering, manufacturing engineering, or related fields. - Strong proficiency with Cadence Allegro PCB Designer. - Expert-level knowledge of PCB component footprint development, package interpretation, and PCB fabrication and assembly manufacturing processes. - Strong understanding of DFM, DFA, DFT methodologies, IPC-7351 standards, IPC Class 2/Class 3 requirements, PCB stackups, via structures, padstacks, and manufacturing tolerances. - Experience interpreting mechanical drawings, package outlines, GD&T, and component specifications.
This role has been open 103 days — well above the 51-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
992
|
Median days open
51 d
|
Median salary
$154k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (992 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 52 | 992 |
| Open roles in the wider Software, Firmware & Systems family | 992 | 6222 · 145 employers |
| Median days open | 67 d | 51 d (+16 d vs this employer) |
| Median salary (USD postings) | — | $154k |
Who's hiring in this category
- Intel Corporation · 76 open roles · median 33 d
- KLA Corporation · 63 open roles · median 47 d
- Teradyne · 57 open roles · median 33 d
- NVIDIA (this employer) · 52 open roles · median 68 d
- Applied Materials · 51 open roles · median 69 d
- AMD · 47 open roles · median 53 d
How we counted: 992 open Hardware Systems Engineering (AI ML Hardware) roles from 104 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.