Senior Package Layout Engineer - Yokneam, Israel
Originally posted 28 September 2026 by the employer.
About the role
This role involves the design of high-speed interconnect systems as a Senior Package Layout Engineer within the IC Packaging design team.
What you'll do
- Collaborate to implement high-speed and PDN design for ASIC packages.
- Develop symbols, pad stack, and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
- Optimize package pin out incorporating system-level trade-offs of pins assignment.
- Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
- Plan, ensure stakeholder management, and lead projects from start to finish.
What you'll need
- B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience.
- 5+ years hands-on experience in Package/PCB Layout and routing, including high-speed design signal integrity practices.
- Experience in substrate layout of wire bond and flip chip packages.
- Knowledge in substrates or board manufacturing process.
- Background with Cadence Virtuoso and APD (Allegro) or SiP and/or other PCB layout tools.
Nice to have
- Knowledge in Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools.
- Familiarity with Skill language (Cadence) and basic parsing abilities (Python/Perl/Shell-scripting).
Skills: IC Packaging design, high-speed Interconnect systems, substrate package routing, Cadence APD (Allegro), flip chip packages
This role has been open 0 days — well below the 41-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
69
|
Median days open
41 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (69 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 69 |
| Median days open | 45 d | 41 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Skills observed across this category: IC Packaging design, high-speed Interconnect systems, substrate package routing, Cadence APD (Allegro), flip chip packages
Who's hiring in this category
- Micron Technology · 12 open roles · median 151 d
- AMD · 6 open roles · median 35 d
- Marvell Technology · 6 open roles · median 21 d
- Broadcom · 5 open roles · median 171 d
- Amazon · 4 open roles · median 20 d
- Intel Corporation · 4 open roles · median 11 d
How we counted: 69 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 25 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.