Senior or Staff Design Verification Engineer - HQ - Vancouver, WA, United States
$160,000 - $190,000 USD yearly
Originally posted 23 September 2026 by the employer.
This role focuses on developing chiplet power delivery technology.
About the role
This role is for an experienced Design Verification Lead to spearhead verification activities for complex SoC/IP designs. You will be developing groundbreaking chiplet power delivery technology.
What you'll do
- Lead verification planning and execution for complex digital and mixed-signal subsystems, defining verification strategies, test scenarios, and coverage goals.
- Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.
- Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements.
- Perform and support Clock Domain Crossing (CDC) verification for async and sync clock-domain interfaces.
- Analyze functional and code coverage and drive coverage closure by identifying verification gaps and developing targeted tests.
- Debug complex RTL, testbench, simulation, and gate-level failures using waveform and log analysis.
What you'll need
- Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
- 10+ years of experience in digital verification of SoCs with proven ownership of subsystems or full-chip verification.
- Solid understanding of digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration.
- Expertise in Verilog, SystemVerilog, UVM and class-based verification methodologies.
- Expertise in constrained-random, coverage-driven verification, regression automation, and verification signoff.
- Experience with industry-standard EDA tools (Synopsys, Cadence).
Nice to have
- Working knowledge of PMIC architectures and power management principles.
- Experience with formal verification techniques.
Skills: SystemVerilog, UVM, constrained-random verification, functional coverage, RTL simulation
This role has been open 23 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | PowerLattice | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1205 |
| Open roles in the wider Digital Design & Verification family | 2 | 3205 · 115 employers |
| Median days open | 23 d | 64 d (−41 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SystemVerilog, UVM, constrained-random verification, functional coverage, RTL simulation
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.