Originally posted 6 August 2026 by the employer.
About the role
Mueon is seeking a Senior Mixed-signal and PHY Design Engineer to lead the design and micro-architecture of high-speed mixed-signal PHY subsystems. The role focuses on designing and integrating DDR-like and SerDes-like PHY IP across architectural, analog, digital, firmware, and packaging domains.
What you'll do
- Lead the design and micro-architecture of mixed-signal PHY subsystems for high-speed interconnects.
- Design high-speed analog circuits for DDR-like and SerDes-like PHYs, including equalization and training circuits.
- Collaborate with system, power delivery, and packaging teams to meet link-level requirements.
- Develop and support digital timing, calibration, and standard or proprietary training architectures.
- Contribute to PHY training and bring-up firmware flows, including validation and silicon debug across multiple generations.
- Interpret and implement electrical and timing specifications such as DDR, UCIe, and related standards.
What you'll need
- M.S. or Ph.D. in Electrical Engineering or equivalent experience.
- 10+ years of experience in mixed-signal circuit and PHY design.
- Familiarity with signal integrity techniques for high-speed interfaces.
- Experience designing and delivering high-speed PHY IPs to production.
- Experience with DDR, SerDes, or advanced die-to-die interconnects.
Nice to have
- Protocol and link layer functionality and requirements of high-speed interconnect standards, especially UCIe3, LPDDR, HBM4, or XSR links.
Skills: PHY, SerDes, DDR, UCIe, mixed-signal
More semiconductor jobs: Signal integrity jobs · Hillsboro jobs
First seen in our index 0 days ago, well below the 61-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
255
|
Median days since first seen
61 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Mueon | All employers we track in this specialty (255 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 255 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1538 · 118 employers |
| Median days since first seen | 0 d | 61 d (+61 d vs this employer) |
| Median salary (USD postings) | n/a | $207k |
Skills observed across this category: PHY, SerDes, DDR, UCIe, mixed-signal
Who's hiring in this category
- Synopsys · 41 open roles · median 39 d
- AMD · 22 open roles · median 47 d
- Cadence Design Systems · 21 open roles · median 155 d
- NVIDIA · 18 open roles · median 216 d
- Qualcomm · 16 open roles · median 89 d
- Apple · 11 open roles · median 5 d
How we counted: 255 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 51 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Analog & Mixed-Signal family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.