Senior Mixed Signal Design Engineer - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 2 July 2026 by the employer — open 70 days.
About the role
This role involves building and implementing high-speed Serdes reaching 80Gbps and beyond. You will work with deep-submicron CMOS and FinFET technology.
What you'll do
- Architect high-speed Serdes and transistor-level builds, pushing data rates to 80Gbps and higher.
- Drive the entire lifecycle from initial concept to layout, verification, and final silicon characterization.
- Optimize complex circuits for peak system performance, balancing noise, power, and loop stability in deep-submicron nodes.
- Partner with layout engineers for strategic floorplanning and high-speed routing mentorship.
- Lead post-silicon bring-up and debugging efforts, translating real-world data into build refinements.
What you'll need
- MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- Minimum 5 plus years of professional Analog Build experience, with a deep portfolio in FinFET and deep-submicron CMOS processes.
- Proficiency in the Cadence Virtuoso environment and simulation tools (Spectre, HSpice, FineSim, or XA).
- Expertise in noise analysis, Monte Carlo simulations, and complex loop stability.
- Experience in high-speed data and/or clock path design.
- Proven ability in the modeling, timing, and functionality of both analog and digital circuits.
Skills: high-speed Serdes, 80Gbps, FinFET, deep-submicron CMOS, silicon characterization
This role has been open 96 days — slightly above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 10 | 217 |
| Median days open | 95 d | 91 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed Serdes, 80Gbps, FinFET, deep-submicron CMOS, silicon characterization
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA (this employer) · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.