Senior Memory Post Silicon Qualification Engineer - CA, Santa Clara, United States
Verification, Validation & Test
Originally posted 31 July 2026 by the employer.
About the role
This role involves owning high-speed memory bring-up, characterization, and qualification on GPU, CPU, and SoC programs within the Silicon Co-Design Group.
What you'll do
- Bring up high-speed memory interfaces (GDDR, LPDDR, HBM) on GPU, CPU, and SoC silicon from first power-on through full PVT characterization.
- Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across the memory controller, PHY, and DRAM device.
- Lead root-cause closure on multi-team memory failures spanning silicon, controller, PHY, package, board SI/PI, firmware, and workload.
- Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, and failure signature detection.
- Partner with pre-Si architecture, design, and DV teams to translate new memory features into targeted post-Si validation plans.
- Work across globally distributed teams including silicon design, PHY, PCB, firmware, software, DRAM vendors, and manufacturing partners.
What you'll need
- B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering (or equivalent experience).
- 10+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.
- Deep protocol and physical-layer understanding of GDDR, LPDDR, or HBM, including training, calibration, IO tuning, timing margin, and vendor-to-vendor behavior differences.
- Strong hands-on lab fundamentals using oscilloscope, DMM, thermal chambers, and protocol analyzers.
- Working knowledge of PCB stack-up, board layout, power planes, and SI/PI guidelines that show up as real memory issues.
- Demonstrated AI-driven workflow built or scaled for memory characterization, margin analysis, or failure triage.
Market context
This role has been open 71 days — slightly above the 66-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 118 |
| Open roles in the wider Silicon Validation & Test family | 97 | 2218 · 113 employers |
| Median days open | 71 d | 66 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 39 d
- AMD · 16 open roles · median 55 d
- NVIDIA (this employer) · 15 open roles · median 72 d
- Graphcore · 10 open roles · median 123 d
- Amazon · 6 open roles · median 42 d
- Micron Technology · 5 open roles · median 213 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.