Originally posted 6 August 2026 by the employer.
About the role
Mueon is hiring a Senior Memory Architect to define and drive the memory architecture for AI platforms. You will solve problems in bandwidth scaling, latency hiding, data orchestration, and memory-compute balance across chip and system boundaries.
What you'll do
- Define memory system architectures for AI/HPC SoCs, including hierarchy, caching, coherence, and data movement.
- Drive architectural tradeoffs across performance, power, area, programmability, and scalability.
- Identify and resolve bottlenecks in bandwidth, latency, and memory efficiency for large-scale AI workloads.
- Develop and guide performance modeling frameworks to evaluate architectural directions.
- Lead cross-functional efforts spanning RTL, physical design, firmware, and system software.
- Debug and root-cause performance gaps across simulation and silicon.
What you'll need
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 8+ years of experience in architecture with a focus on memory systems or data movement.
- Strong experience with performance modeling, simulation, and workload analysis.
- Demonstrated impact on shipped silicon or large-scale systems.
- Deep expertise in memory system architecture, such as cache hierarchies, interconnects, coherence, MMU, prefetching, or dataflow systems.
Nice to have
- Experience with AI/ML workloads and data center-scale systems.
- Familiarity with HBM, DDR, CXL, or emerging memory technologies.
- Experience with memory coherence protocols in large-scale systems.
- Background in hardware/software co-design and system architecture.
- Strong coding and modeling skills in C++, Python, or similar languages.
Skills: memory architecture, cache hierarchy, coherence, performance modeling, HBM
More semiconductor jobs: SoC design jobs · Hillsboro jobs
First seen in our index 0 days ago, well below the 82-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
486
|
Median days since first seen
82 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Mueon | All employers we track in this specialty (486 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 486 |
| Open roles in the wider Digital Design & Verification family | 8 | 3506 · 120 employers |
| Median days since first seen | 0 d | 82 d (+82 d vs this employer) |
| Median salary (USD postings) | n/a | $230k |
Skills observed across this category: memory architecture, cache hierarchy, coherence, performance modeling, HBM
Who's hiring in this category
- Qualcomm · 79 open roles · median 92 d
- NVIDIA · 67 open roles · median 84 d
- AMD · 39 open roles · median 71 d
- Arm Holdings · 29 open roles · median 14 d
- Apple · 28 open roles · median 15 d
- Micron Technology · 20 open roles · median 114 d
How we counted: 486 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.