Senior Mechanical Engineer (Memory Test, Agoura Hills, CA)
$121,700 - $214,200 USD yearly
Originally posted 21 October 2026 by the employer.
About the role
The Senior Mechanical Engineer develops detailed electro-mechanical design solutions from product requirements, performs DFM with vendors, prepares fabrication drawings and BOMs, and builds initial prototypes for validation and design verification. The role focuses on signal delivery design within the Memory Test group.
What you'll do
- Collaborate across Hardware, Software, Signal Integrity, and Mechanical engineering teams to establish requirements and design documentation for signal delivery projects. - Manage signal delivery project schedules across design, prototyping/testing, and New Product Introduction phases. - Create design concepts, develop Statements of Work for third-party vendors, and participate in design reviews with architects and vendors. - Coordinate with signal delivery architects to create test plans validating signal integrity requirements and interpret test results. - Create and maintain part numbers, bills of material (BOMs), assembly drawings, calculations, simulation results, and Engineering Change Notices (ECNs). - Build initial prototypes of proposed designs to complete validation and execute design verification.
What you'll need
- BS or BSME or an equivalent degree and 5 or more years of relevant experience with electro-mechanical design. - Familiarity with Solidworks (or similar) and PDM tools. - Familiarity with sheet metal and machined part design. - Familiarity with stress/strain analysis and FEA. - Experience preparing presentations and design proposals for remote teams using collaboration tools.
Nice to have
- Familiarity with electrical connector design for power delivery and high speed signal delivery. - Familiarity with measuring connector performance metrics such as lifecycle, contact resistance, and current carrying capacity. - Familiarity with signal integrity concepts for single ended and differential signaling, including insertion loss, return loss, and crosstalk. - Experience with coaxial cable mass termination techniques. - Understanding of basic PCB design concepts, including material choice, high speed signal routing, and manufacturing techniques. - Previous experience with Cadence Allegro or a similar PCB CAD tool.
This role has been open 0 days — well below the 51-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
992
|
Median days open
51 d
|
Median salary
$154k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (992 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 61 | 992 |
| Open roles in the wider Software, Firmware & Systems family | 108 | 6296 · 145 employers |
| Median days open | 34 d | 51 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $154k |
Who's hiring in this category
- Intel Corporation · 76 open roles · median 33 d
- KLA Corporation · 63 open roles · median 47 d
- Teradyne (this employer) · 57 open roles · median 33 d
- NVIDIA · 52 open roles · median 68 d
- Applied Materials · 51 open roles · median 69 d
- AMD · 47 open roles · median 53 d
How we counted: 992 open Hardware Systems Engineering (AI ML Hardware) roles from 104 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.