Senior Manager, Test, Manufacturability, Reliability and Quality - CA, Santa Clara, United States
Originally posted 28 July 2026 by the employer.
Lead the Test, Manufacturability, Reliability & Quality team across GPU, SoC, and CPU programs spanning SLT, BLT, and HTOL flows.
About the role
Lead the Test, Manufacturability, Reliability & Quality (TMRQ) organization within the Silicon Co-Design Group, overseeing programs from first power-on through high-volume production. The scope includes production test development across SLT, BLT, control run flows, and system reliability stress (HTOL) for GPU, SoC, and CPU silicon programs.
What you'll do
- Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack control runs, and system reliability stress (HTOL) across GPU, SoC, and CPU silicon programs. - Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving cross-functional root-cause analysis across design, DFT, ATE, package, software/firmware, and manufacturing. - Convert integration signals including CR fallout, yield data, SHTOL/CHTOL metrics, RMA trends, and customer escalations into decision-ready recommendations for POR and QS/PS gates. - Refine closed-loop methodologies to improve cycle time, first-pass yield, test-time reduction, escape rate, and DPPM. - Own manufacturing issues at platform and board levels, conducting root-cause analysis on field returns to implement preventive screening and process adjustments. - Hire, develop, and retain managers and lead engineers across multiple geographies, guiding first-line managers into independently operating leaders.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering, or related field (or equivalent experience). - 12+ years of experience in production test, system validation, post-silicon integration, or reliability engineering in a high-volume silicon environment, including 5+ years in management. - Strong EE fundamentals across DFT, BIST, digital design, computer architecture, fault models, fault analysis, power and timing analysis, sampling, and statistics. - Hands-on expertise across the production test stack (ATE, SLT, BLT), Control Run methodology, FinFET-class manufacturing processes, and PVT/binning dependencies.
This role has been open 161 days — well above the 113-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
185
|
Median days open
113 d
|
Median salary
$129k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (185 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 185 |
| Open roles in the wider Silicon Validation & Test family | 85 | 2238 · 112 employers |
| Median days open | 88 d | 113 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $129k |
Who's hiring in this category
- Teradyne · 14 open roles · median 118 d
- Qualcomm · 12 open roles · median 113 d
- Renesas Electronics · 12 open roles · median 106 d
- Infineon Technologies · 9 open roles · median 121 d
- Marvell Technology · 9 open roles · median 121 d
- onsemi · 8 open roles · median 135 d
How we counted: 185 open Silicon Test Engineering (Silicon Validation) roles from 55 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.