Senior Manager, Soc Power Modeling - TX, Austin, United States
$175,000 - $300,000 USD yearly
Originally posted 27 April 2026 by the employer.
Own and drive the power modeling framework for Client and handheld products within the AMD Computing and Graphics group.
About the role
Power architects guide SoCs from early concept stages through design execution and post silicon within the SOC Architecture team in the AMD Computing and Graphics group. This role owns and drives the power modeling effort for Client and handheld products across architecture definition, IP design, firmware, software, and silicon validation.
What you'll do
- Work with hardware and firmware/software power architects to integrate the power and performance modeling framework for rapid prototyping and what-if architectural analysis. - Lead power modeling of complex use case scenarios across the SoC roadmap, correlating pre-silicon estimates at each maturity milestone to tape-out PTPX numbers, emulation, and post-silicon silicon attainment. - Perform detailed workload analysis across IP, subsystem, and SoC levels to improve power efficiency, performance per watt, and battery life. - Define the power roadmap, competitive targets, and bounding box workloads in collaboration with internal teams, customers, and industry standards. - Coordinate across SoC architecture, IP design, systems engineering, and product engineering to drive power feature enablement from concept to silicon attainment. - Lead modeling design of experiments towards an integrated power-performance framework for power-perf improvements, voltage margining, and feature ROI analysis.
What you'll need
- Bachelor's or Master's degree in a related engineering discipline. - Commercial engineering experience in SoC power modeling and architecture. - Experience with power evaluation, modeling, simulation, and silicon attainment through emulation and post-silicon correlation. - Demonstrated technical experience analyzing workloads and optimizing computing systems for performance and power efficiency. - Experience working with firmware algorithm and software driver teams for power feature enablement.
Nice to have
- Understanding of semiconductor power delivery including on-die, substrate, silicon interposer, and PCB power delivery. - Experience with power integrity and signal integrity analysis, droop management/mitigation, and capacitor performance. - Experience architecting SoC power features and low power states to improve battery life. - C/C++ programming and scripting automation capabilities. - General familiarity with microprocessor or PC architecture.
Skills: power architect, SOC Architecture, workload analysis, power efficiency, bounding box workloads
This role has been open 177 days — well above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
477
|
Median days open
79 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (477 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 477 |
| Open roles in the wider Digital Design & Verification family | 251 | 3328 · 115 employers |
| Median days open | 74 d | 79 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: power architect, SOC Architecture, workload analysis, power efficiency, bounding box workloads
Who's hiring in this category
- Qualcomm · 80 open roles · median 83 d
- NVIDIA · 56 open roles · median 67 d
- Apple · 37 open roles · median 17 d
- AMD (this employer) · 36 open roles · median 74 d
- Arm Holdings · 27 open roles · median 122 d
- Micron Technology · 21 open roles · median 101 d
How we counted: 477 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.