Senior Manager, Silicon Speed Productization — Silicon Co-Design Group - CA, Santa Clara, United States
$232,000 - $368,000 USD yearly
Originally posted 29 September 2026 by the employer.
About the role
This role leads the Silicon Speed Productization team, focusing on simulation-to-silicon speed correlation and determining product frequency across various conditions. This team identifies prediction divergences, drives root-cause closure, and establishes technical bases for product limits, guardbands, binning, and production sign-off.
What you'll do
- Own speed characterization and correlation from pre-silicon planning through production sign-off across GPU, CPU, and SoC programs.
- Drive root-cause closure when a frequency corner does not hold, minimum operating voltage is too high, or a critical path escapes timing analysis.
- Refine methodologies for silicon margining, process-voltage-temperature characterization, guardbanding, aging, and speed binning.
- Feed measured-silicon insights back into timing models, critical-path predictions, test content, and design practices.
- Convert characterization data, model deltas, and yield trends into decision-ready options for leadership.
- Build closed-loop data, automation, and AI-assisted workflows for test orchestration, anomaly detection, triage, and reporting.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering (or equivalent experience).
- 12+ overall years of experience in silicon characterization, post-silicon validation, timing or performance analysis.
- 5+ years leading technical teams.
- Proven management experience developing senior engineers and first-line managers.
- Deep technical foundation in digital design, computer architecture, static timing analysis, critical-path behavior, clocking, power and timing interactions, semiconductor process variation, sampling, and statistics.
- Hands-on expertise with silicon speed characterization, simulation-to-silicon correlation, voltage-frequency margining, guardbanding, and process-voltage-temperature and binning dependencies for high-performance silicon.
- Demonstrated ability to drive ambiguous, system-level issues to root-cause closure.
- Proficiency with data-analysis and automation tools such as Python, JMP, SQL.
Skills: silicon characterization, post-silicon validation, timing analysis, frequency corner, guardbanding, P-V-T
This role has been open 11 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
398
|
Median days open
41 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (398 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 398 |
| Open roles in the wider Silicon Validation & Test family | 94 | 2196 · 111 employers |
| Median days open | 21 d | 41 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: silicon characterization, post-silicon validation, timing analysis, frequency corner, guardbanding, P-V-T
Who's hiring in this category
- AMD · 57 open roles · median 42 d
- Micron Technology · 39 open roles · median 32 d
- Qualcomm · 34 open roles · median 27 d
- NVIDIA (this employer) · 24 open roles · median 20 d
- Graphcore · 21 open roles · median 115 d
- Microchip Technology · 20 open roles · median 67 d
How we counted: 398 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.