Senior Manager, Post-Silicon Bring-Up - CA, Santa Clara, United States
Verification, Validation & Test
Originally posted 28 July 2026 by the employer.
About the role
This role leads post-silicon bring-up and productization for complex, high-performance silicon products, driving execution from first power-on through debug, validation, production readiness, and sustained product ramp.
What you'll do
- Lead end-to-end post-silicon execution from first-silicon power-on through production qualification and volume ramp.
- Drive technical and program execution across architecture, design, verification, firmware, software, boards, systems, test, product engineering, and operations.
- Lead the bring-up operating model, including priorities, staffing, issue triage, metrics, and closure plans for high-risk silicon issues.
- Lead resolution of complex post-silicon issues involving power, clocks, reset, boot, interfaces, performance, reliability, and hardware-software interactions.
- Drive silicon characterization and reliability qualification plans through execution, including assessments of electrical, speed, power, thermal, and environmental conditions.
- Establish and continuously improve bring-up methodology, test planning, debug readiness, lab readiness, and execution processes.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 12+ years of overall experience and 5+ years of management experience, including leadership in post-silicon bring-up, validation, debug, or productization for complex SoCs, GPUs, ASICs, or systems.
- Proven experience leading teams through first-silicon bring-up, issue triage, debug closure, and transition to production.
- Deep technical understanding of digital design, computer or system architecture, power, timing, clocking, reset, noise, fault analysis, and hardware-software interactions.
- Strong experience with post-silicon debug and validation flows, including lab execution, test planning, and data-driven issue management.
- Familiarity with driving silicon characterization and reliability qualification, including electrical and process-voltage-temperature characterization, HTOL, ELFR, package qualification, and AEC-Q100.
Nice to have
- Experience leading bring-up for both SoC- and GPU-class silicon or highly integrated platform programs.
- Hands-on experience with first power-on, system bring-up, silicon characterization, binning, reliability qualification, or production ramp.
- Experience building bring-up methodologies, debug infrastructure, or validation frameworks.
- Strong background in firmware, low-level software, or hardware-software co-debug for complex systems.
- Experience driving pre-silicon execution, including multi-functional planning through design, verification, and tapeout readiness.
Market context
This role has been open 81 days — well above the 66-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 118 |
| Open roles in the wider Silicon Validation & Test family | 97 | 2219 · 113 employers |
| Median days open | 72 d | 66 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 39 d
- AMD · 16 open roles · median 55 d
- NVIDIA (this employer) · 15 open roles · median 72 d
- Graphcore · 10 open roles · median 123 d
- Amazon · 6 open roles · median 42 d
- Micron Technology · 5 open roles · median 213 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.