Senior Manager, ASIC Chip Engineering - CA, Santa Clara, United States
$232,000 - $368,000 USD yearly
Originally posted 6 August 2026 by the employer.
Drive development of future SoC processors.
About the role
This role is responsible for driving the execution of SOCs from concept to production. You will coordinate activities across IP design, integration, DFT, physical design, VLSI, emulation, software, and operation teams for successful productization with first silicon.
What you'll do
- Drive the execution of SOCs from concept to production. - Define and track project achievements and dependencies across multi-functional teams. - Coordinate activities of IP design, integration, DFT, physical design, VLSI, emulation, software, and operation teams. - Identify and characterize key technical risks and work with engineering and management to identify mitigation strategies. - Provide technical leadership to the team. - Identify and implement key data analytics and automation flows using various programming languages. - Drive after action reviews for continuous improvement of project workflows and execution.
What you'll need
- BSEE or equivalent experience. - Minimum of 10 overall years of proven experience in chip development. - At least 5+ years managing an SoC or a key sub-system. - Experience in development cycle of graphics processing, memory, and I/O sub-systems in SOC chips. - Deep knowledge of the entire chip life cycle phases from concept to production, including markets, competition, architecture, front-end flows (micro-architecture, low-power design, RTL coding, verification, emulation), back-end flows (physical design, clock/reset distribution, DFT), silicon bring-up, reliability, and qualifications.
Nice to have
- Strong algorithm development and programming skills. - Good understanding of the client and automotive markets. - Experience with safety standards such as ISO26262 and delivering safety hardware and software.
Skills: ASIC, SoC, chip development, productization, ISO26262
This role has been open 71 days — well above the 47-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
47 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (175 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 175 |
| Median days open | 34 d | 47 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: ASIC, SoC, chip development, productization, ISO26262
Who's hiring in this category
- Qualcomm · 25 open roles · median 47 d
- NVIDIA (this employer) · 20 open roles · median 35 d
- AMD · 19 open roles · median 26 d
- Synopsys · 14 open roles · median 47 d
- Arm Holdings · 10 open roles · median 84 d
- Astera Labs · 6 open roles · median 68 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 49 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.