Senior Manager - Analog Design - CA, Santa Clara, United States
Originally posted 17 September 2026 by the employer.
Manage the Memory I/O design team supporting future LPDDR IPs.
About the role
This role involves managing the Memory I/O design team, supporting the definition, specification, system simulation, and implementation of future LPDDR IPs. The focus includes circuit architecture and design of high-speed analog and digital blocks.
What you'll do
- Manage and contribute to the definition of circuit architecture and design implementation of low power, area efficient circuits for LPDDR PHYs.
- Work closely with Analog Mixed Signal design, Digital Design, Firmware, and Design Verification to ensure optimal PHY architecture and algorithm implementation.
- Manage execution and deliverables across customers and stakeholders.
- Develop models for link-level statistical performance simulation of the PHY and apply them to design development and optimization.
- Document micro-architecture and algorithms, and guide Analog, Digital, Firmware, and Verification teams on circuit training and verification.
- Participate and contribute to the definition of development flows that improve efficiency and quality of execution.
What you'll need
- Bachelor, Master, or Ph.D. degree in computer engineering/Electrical Engineering.
- Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
- Solid knowledge of industry-standard tools and practices for PHY modeling, including abstracted models (Matlab/Simulink) and Verilog/AMS-based.
- Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
- Ability to analyze RTL or FW code supporting custom circuit implementation.
Nice to have
- Proven track record of successfully leading execution of multiple PHY designs with very good Silicon results.
- Proven successful track record in circuit-architecture and modeling for High Speed IOs.
- Team management experience leading multiple IPs from design to production.
Skills: Memory I/O design, LPDDR IPs, high-speed analog, digital blocks, link performance simulations
This role has been open 25 days — well below the 80-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
80 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (244 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 38 | 1414 · 105 employers |
| Median days open | 37 d | 80 d (−43 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Memory I/O design, LPDDR IPs, high-speed analog, digital blocks, link performance simulations
Who's hiring in this category
- AMD (this employer) · 31 open roles · median 40 d
- Synopsys · 31 open roles · median 28 d
- Cadence Design Systems · 19 open roles · median 186 d
- Qualcomm · 19 open roles · median 60 d
- Micron Technology · 13 open roles · median 73 d
- Apple · 12 open roles · median 14 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.