Senior Leader, Signal and Power Integrity/Systems Architecture (High-Speed Interconnects) - Multiple locations

Originally posted 18 August 2026 by the employer.

About the role

This role involves defining, developing, and productizing electrical and optical interconnect technologies for AI, hyperscale datacenter, networking, and HPC systems.

What you'll do

• Lead system design and performance closure across SerDes and PHY architectures, EIC/PIC integration, and optical engines.
• Own SI/PI methodology and end-to-end link analysis including channel budgeting, COM analysis, jitter, and crosstalk.
• Drive electrical-optical DSP architecture and algorithm development including TX/RX equalization, CDR, and adaptive filtering.
• Develop system-level models and architecture tradeoff studies spanning bandwidth, reach, power, latency, reliability, manufacturability, cost, and scalability.
• Provide technical leadership across silicon, package, optics, platform, and software organizations while driving technology roadmaps.

What you'll need

• Demonstrated success productizing 112G and/or 224G PAM4 electrical and optical communication systems.
• Deep expertise in High-speed SerDes architectures, Electrical-optical DSP algorithms, and PAM4 communication systems.
• Deep expertise in Signal Integrity (SI) and Power Integrity (PI), EIC/PIC co-design, and heterogeneous integration.
• Hands-on experience with ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, Lumerical, Zemax, Verilog-A, SystemVerilog, COM analysis tools, and IBIS-AMI modeling.
• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 10+ years of System/Package Design/Technology Engineering experience.

Nice to have

• MS or PhD in Electrical Engineering, Optical Engineering, Physics, or a related discipline.
• 15 years of experience developing high-speed communication, networking, or optical interconnect products.
• Experience developing and productizing 224G electrical and optical interconnect solutions.
• Experience with CPO, NPO, CPC, NPC, flyover copper, flyover optical, silicon photonics, and EIC/PIC integration.
• Familiarity with Ethernet, PCIe, UALink, NVLink, OIF CEI, IEEE 802.3, and emerging AI interconnect standards.
• Experience with chiplets, UCIe, silicon photonics, 2.5D/3D integration, and advanced packaging technologies.
• Track record influencing industry standards, technology roadmaps, and large cross-functional architecture decisions.
• Proven success leading and mentoring senior technical teams across multiple engineering disciplines.