Senior Lead Engineer - Design Verification

Lead verification architecture and UVM environments for FPGA and programmable SoC subsystems.

Originally posted 5 November 2026 by the employer.

About the role

Altera is seeking a Senior Lead Engineer - Design Verification to provide technical leadership for the verification of FPGA, programmable SoC, and platform solutions. This individual-contributor role shapes verification architecture, methodology, and execution for digital subsystems and full-chip integrations.

What you'll do

• Lead verification architecture, planning, and execution for FPGA, programmable SoC, and infrastructure subsystems across block, subsystem, and full-chip levels.
• Define verification plans translating architectural specifications into measurable functional, performance, resilience, and coverage objectives.
• Architect and develop reusable SystemVerilog and UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models.
• Drive verification closure using functional, code, assertion, and cross coverage against defined exit criteria.
• Lead root-cause debug of simulation, integration, and system-level failures across design, verification, firmware, and validation teams.
• Collaborate with emulation, FPGA prototyping, physical design, CAD, firmware, and post-silicon teams through implementation and bring-up.

What you'll need

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, with 15+ years of relevant design verification experience in FPGA, ASIC, SoC, or semiconductor products.
• Deep expertise in SystemVerilog and UVM, including constrained-random verification, assertions, self-checking testbenches, functional coverage, and coverage-driven closure.
• Proven experience creating reusable verification IP, UVM frameworks, and testbench components adopted across multiple blocks, teams, or programs.
• Experience verifying high-performance digital architectures such as networking datapaths, memory subsystems, on-chip interconnect, PCIe/CXL, Ethernet, high-speed I/O, or programmable acceleration.
• Technical background in RTL design, microarchitecture, simulation debug, regression management, test automation, and hardware development flows.

Nice to have

• Experience verifying FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience with C/C++, SystemC, Python, Tcl, Perl, or shell scripting for reference models and testbench infrastructure.
• Experience with full-chip verification, processor-based test development, firmware/software co-verification, or post-silicon debug.

Skills: SystemVerilog, UVM, Constrained-Random, Coverage, FPGA

More semiconductor jobs: Altera jobs · Verification engineer jobs · San Jose jobs