$231,500 - $330,000 USD yearly
Originally posted 4 November 2026 by the employer.
About the role
Altera is seeking a Senior Lead Engineer, Design and Architecture to provide technical leadership for the architecture and development of silicon and platform subsystems across its programmable device portfolio. This senior individual-contributor role defines SoC and interconnect solutions, driving architectural and design decisions from concept through production silicon.
What you'll do
- Define system, subsystem, and microarchitecture for SoC, ASIC, and FPGA-adjacent platforms, focusing on interconnect, data movement, memory hierarchy, and compute or networking subsystems.
- Lead architecture exploration and execute tradeoffs across performance, power, area, bandwidth, latency, reliability, scalability, cost, and schedule.
- Develop architectural specifications, performance models, and implementation plans across hardware, firmware, software, and validation teams.
- Guide architecture and design decisions across the silicon lifecycle: concept, microarchitecture, RTL, integration, verification, emulation, implementation, bring-up, and performance debug.
- Deliver hands-on technical leadership for on-chip networks, routing and arbitration, flow control, cache or memory-coherency mechanisms, memory subsystems, and high-speed interfaces.
- Partner across design, verification, physical design, DFT, firmware, software, product engineering, and manufacturing teams to preserve architectural intent through silicon validation.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, with 15+ years of experience in semiconductor, ASIC, SoC, or FPGA product development.
- Demonstrated experience defining and delivering complex silicon architectures from concept through production, spanning architecture, microarchitecture, RTL design, verification, integration, and post-silicon validation.
- Deep expertise in on-chip networks, coherent or non-coherent interconnect, memory hierarchy, cache coherency, high-performance networking datapaths, packet processing, or infrastructure-class SoC design.
- Strong understanding of architectural tradeoffs involving bandwidth, latency, congestion, throughput, power, area, timing, and reliability.
- Experience collaborating across the silicon development lifecycle with design, verification, emulation, physical design, DFT, firmware/software, and post-silicon teams.
Nice to have
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience delivering advanced-node, high-complexity SoCs or ASICs into production for networking, cloud, AI/ML, communications, storage, security, or data-center infrastructure applications.
- Experience architecting scalable Network-on-Chip or fabric solutions, including topology, routing, arbitration, quality of service, traffic management, credit-based flow control, and performance analysis.
- Experience with memory systems, cache hierarchy, coherency protocols, HBM/DDR integration, or high-bandwidth data movement.
- Working knowledge of RTL and verification methodologies such as SystemVerilog, simulation, formal verification, emulation, or equivalence checking, as well as familiarity with synthesis, static timing, and implementation flows.
- Experience with architecture modeling, performance analysis, Python-based automation, or AI-assisted engineering workflows.
- Experience with programmable logic devices, heterogeneous SoC platforms, or the integration of hard and soft IP.
Skills: SoC architecture, microarchitecture, interconnect, NoC, cache coherency
More semiconductor jobs: Altera jobs · SoC design jobs · San Jose jobs
This role has been open 0 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
490
|
Median days open
76 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (490 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 490 |
| Open roles in the wider Digital Design & Verification family | 23 | 3473 · 120 employers |
| Median days open | 35 d | 76 d (−41 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SoC architecture, microarchitecture, interconnect, NoC, cache coherency
Who's hiring in this category
- Qualcomm · 78 open roles · median 89 d
- NVIDIA · 62 open roles · median 77 d
- Apple · 52 open roles · median 26 d
- AMD · 37 open roles · median 70 d
- Arm Holdings · 28 open roles · median 7 d
- Micron Technology · 21 open roles · median 111 d
How we counted: 490 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.