Senior Lead Design Engineer - RTL Design

Originally posted 4 November 2026 by the employer.

About the role

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands-on technical leadership for the RTL architecture, design, integration, and delivery of FPGA and programmable SoC solutions.

What you'll do

• Lead RTL architecture, microarchitecture, and implementation for FPGA, programmable SoC, and infrastructure-class subsystems, emphasizing high-throughput datapaths, memory access, interconnect, and programmable acceleration.
• Own RTL design for critical blocks and subsystem integrations, ensuring logic meets performance, power, area, and timing objectives.
• Define design specifications, interface contracts, clocking and reset strategies, performance targets, and implementation plans.
• Establish and advance RTL design methodologies, including coding standards, lint, CDC/RDC, synthesis, formal checks, and automation.
• Partner with design verification to shape verification strategy, review test plans and coverage, triage failures, and drive closure of pre-silicon issues.
• Collaborate with physical design, CAD, DFT, emulation, FPGA prototyping, board, firmware, and software teams to maintain RTL intent through timing closure and validation.

What you'll need

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development.
• Demonstrated technical leadership delivering complex digital designs from architecture and microarchitecture through RTL, verification, implementation, and hardware validation.
• Deep hands-on expertise in Verilog and/or SystemVerilog RTL development, synthesis, lint, CDC/RDC, formal or equivalence checking, and timing constraints.
• Proven experience designing high-performance digital subsystems, such as data-processing pipelines, memory controllers, on-chip interconnect, PCIe/CXL, Ethernet, or programmable acceleration engines.
• Strong understanding of architectural and RTL-level tradeoffs involving bandwidth, latency, throughput, power, area, and timing.

Nice to have

• Experience designing RTL for FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience building, maintaining, or deploying reusable RTL IP across multiple products, technology nodes, or programs.
• Experience with high-bandwidth memory architectures, packet buffering, lookup or classification engines, flow control, or high-speed connectivity subsystems.
• Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
• Proficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.
• A record of technical leadership through patents, publications, standards contributions, or sustained methodology innovation.

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