Senior Lead Design Engineer

Originally posted 4 November 2026 by the employer.

About the role

Altera is seeking a Senior Lead Design Engineer to provide hands-on technical leadership for the architecture, design, and delivery of FPGA and programmable SoC solutions. The role focuses on the definition and implementation of high-performance digital logic and reusable IP for programmable devices and platform solutions.

What you'll do

• Lead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems, emphasizing high-throughput datapaths, connectivity, interconnect, memory access, or programmable acceleration.
• Define technical requirements, interfaces, architectural specifications, and implementation plans aligned with hardware, firmware, software, and validation objectives.
• Own critical blocks and subsystems through the development lifecycle, including RTL implementation, synthesis, integration, verification support, timing closure, bring-up, and performance characterization.
• Drive technical tradeoffs across performance, power, area, latency, bandwidth, reliability, scalability, cost, and schedule.
• Partner with architecture, design verification, physical design, DFT, CAD, firmware, emulation, FPGA prototyping, and post-silicon teams.
• Lead resolution of complex cross-functional design and system issues, including root-cause analysis, debug strategy, and technical decision-making.

What you'll need

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development.
• Technical leadership delivering complex digital subsystems or products from system architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.
• Hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design practices.
• Experience with high-performance digital architectures such as networking or packet-processing datapaths, offload or acceleration engines, PCIe/CXL, Ethernet, DDR/HBM memory subsystems, high-speed interfaces, or on-chip interconnect.
• Understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs in advanced digital systems.
• Experience leading design execution across multiple functional blocks or chip-level integration, including planning, risk management, and schedule alignment.

Nice to have

• Experience in FPGA architecture, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience building or maintaining reusable design IP deployed across multiple products, programs, or technology nodes.
• Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
• Proficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.
• Experience leading teams or serving as a senior technical mentor in a matrixed engineering environment.
• Record of innovation through patents, publications, standards contributions, or technical thought leadership.

Skills: SystemVerilog, RTL design, microarchitecture, synthesis, SoC

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