Senior IP Verification Engineer - Chandler, Arizona, United States
$161,500 - $218,500 USD yearly
Originally posted 23 July 2026 by the employer.
About the role
Arm's Solution Engineering division is seeking a verification engineer to develop testbenches and test suites for products across Enterprise, Auto, and Client markets.
What you'll do
- Write test plans and complete functional verification to required quality levels and schedules. - Develop IP features that enable reconfigurable designs. - Partner with design teams to review microarchitectural specifications and debug issues. - Collaborate with cross-functional design and verification engineers.
What you'll need
- Bachelor's degree or higher in Computer Science, Electrical/Computer Engineering, or a related field. - Experience in verification of complex subsystems or SoCs across test plan creation, testbench implementation, test case development, documentation, and support. - Experience with front-end verification tools including dynamic simulation tools, static simulation tools, UPF, and debuggers such as Questa, VCS, Jasper Gold, and Verdi. - Hands-on experience with coverage closure including functional, toggle, and code coverage. - Experience with reconfigurable IP or subsystem design.
Nice to have
- Object-oriented programming concepts. - Experience with ARM-based designs or ARM System Architectures. - Understanding of OTP/Fuse usage models and JTAG/TAP protocols. - Scripting experience in Perl, Python, or another scripting language. - Experience with SoC system debug methodologies. - Familiarity with DFT methodologies such as RTL testability, scan insertion, and OCC.
Skills: test plans, functional verification, testbench, UPF, Coverage
This role has been open 87 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1201 |
| Open roles in the wider Digital Design & Verification family | 104 | 3224 · 116 employers |
| Median days open | 104 d | 66 d (+38 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: test plans, functional verification, testbench, UPF, Coverage
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.