Senior HSIO Digital Design Engineer - San Jose, California, United States
Samsung Semiconductor
San Jose, California, United States
3 months ago
Digital Design & SoC Architecture
$138,000 USD yearly
Originally posted 31 July 2026 by the employer.
About the role
This role involves specializing in digital design for die-to-die (chiplet) interfaces or similar high-speed I/O technologies.
What you'll do
- Develop High-Speed I/O PHY IP.
- Understand high-speed serial interconnect protocols.
- Collaborate with system and analog teams on digital-on-top development flows.
- Understand Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
What you'll need
- BS in Electrical Engineering with 5+ years of experience, MS with 3+ years of experience, or PhD in Electrical Engineering.
- Hands-on experience in High-Speed I/O PHY IP development.
- Strong understanding of end-to-end digital design flow.
- Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link.
- Familiarity with HSIO PHY layers protocols and architectures.
Market context
This role has been open 78 days — well above the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1037
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (1037 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1037 |
| Open roles in the wider Digital Design & Verification family | 13 | 3201 · 115 employers |
| Median days open | 60 d | 60 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 64 d
- Synopsys · 86 open roles · median 32 d
- AMD · 71 open roles · median 38 d
- Analog Devices · 47 open roles · median 50 d
- NVIDIA · 44 open roles · median 60 d
- NXP Semiconductors · 42 open roles · median 86 d
How we counted: 1037 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Samsung Semiconductor
San Jose, California, United States
On-site
$138,000 USD yearly
3 months ago