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NVIDIA

Senior High Speed SerDes Validation Engineer - CA, Santa Clara, United States

NVIDIA US, CA, Santa Clara, United States 13 days ago
Analog & Mixed-Signal Design

$168,000 - $310,500 USD yearly

Originally posted 28 September 2026 by the employer.

About the role

What you'll do

  • Own validation of products from start to finish, including test plan development, automation, and bug resolution.
  • Collaborate with ODMs, component suppliers, and QA teams to ensure test coverage.
  • Coordinate internal and external teams across different time zones.
  • Develop system-level stress and performance testing strategies using Deep Learning/AI applications.

What you'll need

  • Ability to work on site in a hardware lab environment 5 days a week.
  • BSEE or BSCE or equivalent experience.
  • 6+ years of experience in validating and debugging complex systems.
  • Experience developing/running real-world workload and factory diagnosis tools.
  • High-speed IO validation experience.
  • Familiarity with lab instrumentations like Oscilloscopes (Digital Multi Meter).
  • High-speed SERDES validation experience (50GBaud/s and above).
  • Strong understanding of DSP-based high-speed SERDES architectures.
  • Coding experience with C/C++, JS, and Python.

Skills: High speed IO validation, SERDES validation, DSP-based high-speed SERDES, lab instrumentations, system level stress, performance testing

Market context

This role has been open 11 days — well below the 77-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category
242
Median days open
77 d
Median salary
$177k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How NVIDIA compares in High-Speed IO/SerDes Design hiring
Metric NVIDIA All employers we track in this specialty (242 roles · 48 employers)
Open roles in this specialty 9 242
Open roles in the wider Analog & Mixed-Signal family 28 1413 · 106 employers
Median days open 183 d 77 d (+106 d vs this employer)
Median salary (USD postings) — $177k

Skills observed across this category: High speed IO validation, SERDES validation, DSP-based high-speed SERDES, lab instrumentations, system level stress, performance testing

Who's hiring in this category

  • AMD · 30 open roles · median 37 d
  • Synopsys · 29 open roles · median 25 d
  • Cadence Design Systems · 19 open roles · median 183 d
  • Qualcomm · 19 open roles · median 58 d
  • Micron Technology · 13 open roles · median 70 d
  • Apple · 12 open roles · median 11 d

How we counted: 242 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.

Apply now
US, CA, Santa Clara, United States
On-site
$168,000 - $310,500 USD yearly
13 days ago

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