Senior Hardware Design Engineer - Austin, Texas, United States
$120,000 USD yearly
Originally posted 18 August 2026 by the employer.
Design component units of the RDU ASIC.
About the role
SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in AI workload acceleration systems. This role focuses on implementing innovative features in hardware that provide unique value to SambaNova, specifically for the RDU.
What you'll do
- Work with principal engineers and architects to author sections of the microarchitecture specification for compute, memory, or networking subsystems.
- Code, integrate, and debug SystemVerilog RTL for assigned blocks through the chip implementation and production lifecycle.
- Meet Power, Performance, and Area (PPA) targets for your blocks using advanced digital design techniques for high-speed design.
- Partner with design verification and physical design engineers to converge on functionality, timing, and area.
- Implement SystemVerilog Assertions (SVA) and run lint, CDC, and LEC flows to check design intent and keep blocks clean.
- Support post-silicon bring-up and debug for the blocks you own.
What you'll need
- Master's degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or Bachelor's degree with 5–7 years.
- Solid foundation in computer architecture and digital logic design.
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
- Experience making design decisions that trade off Power, Performance, and Area (PPA).
- Working knowledge of industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
- Proficiency with industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).
- Experience implementing SystemVerilog Assertions (SVA) to check design intent.
- Scripting skills in Python and Linux shell.
Nice to have
- Exposure to a full ASIC development cycle through tapeout and production silicon.
- Experience with low-power design techniques (clock gating, DVFS) at advanced process nodes.
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation.
This role has been open 59 days — slightly above the 50-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
966
|
Median days open
50 d
|
Median salary
$156k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (966 roles · 102 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 966 |
| Open roles in the wider Software, Firmware & Systems family | 23 | 6157 · 145 employers |
| Median days open | 59 d | 50 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $156k |
Who's hiring in this category
- Intel Corporation · 74 open roles · median 35 d
- KLA Corporation · 65 open roles · median 43 d
- Teradyne · 57 open roles · median 29 d
- NVIDIA · 52 open roles · median 67 d
- Applied Materials · 50 open roles · median 65 d
- AMD · 47 open roles · median 49 d
How we counted: 966 open Hardware Systems Engineering (AI ML Hardware) roles from 102 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.