Senior Full Chip Layout Engineer
Originally posted 18 September 2026 by the employer — open 1 day.
About the role
This role involves performing physical layout for full-chip level integration, pinning, and bump route. You will be responsible for chip layout from the floorplanning stage through tape-out for high-speed communication devices.
What you'll do
- Perform physical layout for full-chip level, integration, pinning, and bump route.
- Work with block owners and project managers to assure high quality convergence in all layout aspects.
- Be responsible for chip layout from the floorplanning stage through tape-out.
What you'll need
- An Electronics Engineer certificate or a B.Sc. in Electrical Engineering.
- 5 years of hands-on Full-chip layout and Physical Verification experience.
- Strong background in Physical Verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes.
- Knowledge in scripts' language: TCL, Unix, and Shell.
- Experience in Linux environments.
- Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).
- Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre).
Skills: Full Chip Layout Engineer, physical layout, full-chip level, floorplanning, tape-out, Physical Verification
This role has been open 0 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
603
|
Median days open
58 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (603 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 603 |
| Open roles in the wider Physical Implementation family | 93 | 1371 · 106 employers |
| Median days open | 43 d | 58 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Full Chip Layout Engineer, physical layout, full-chip level, floorplanning, tape-out, Physical Verification
Who's hiring in this category
- Qualcomm · 108 open roles · median 41 d
- Broadcom · 38 open roles · median 68 d
- NVIDIA (this employer) · 38 open roles · median 49 d
- AMD · 35 open roles · median 38 d
- Synopsys · 27 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 45 d
How we counted: 603 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.