Senior FPGA Design Engineer (MTD, San Jose, CA)
$170,400 - $272,600 USD yearly
Originally posted 8 August 2026 by the employer. Relisted by the employer on 17 September 2026.
Develop FPGA solutions for Flash and DRAM test instrumentation.
About the role
This role involves developing and implementing FPGA solutions to support memory test instrumentation within Teradyne's Memory Test Division (MTD).
What you'll do
- Architect and implement FPGA solutions for Flash and DRAM test instrumentation. - Provide technical guidance to junior engineers. - Translate abstract concepts and customer requirements into reliable, extensible, and supportable designs. - Assist in the maintenance and extension of existing FPGA designs. - Maintain schedule commitments and deliver high quality end products.
What you'll need
- B.S. or M.S. in Electrical Engineering or closely related discipline and 8+ years of relevant work experience. - Experience with Digital Design and Architecture. - RTL coding, synthesis, timing closure and lab validation. - Experience with Static Timing Analysis of ASICs or FPGAs. - Experience with digital simulation testbench creation. - Experience with C or C++. - Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.
Nice to have
- FPGA Transceiver based design experience. - Experience with DRAM and Flash Memory interfaces. - Experience with Intel/Xilinx FPGA tool flows. - Proficiency with Verilog HDL Language. - Familiarity with UVM Methodology. - Scripting languages experience. - Linux and Windows operating systems experience. - Familiarity with ATE instrumentation.
This role has been open 70 days — well above the 60-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
102
|
Median days open
60 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (102 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 102 |
| Median days open | 70 d | 60 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- Altera · 30 open roles · median 59 d
- AMD · 12 open roles · median 50 d
- Teradyne (this employer) · 10 open roles · median 69 d
- Qualcomm · 8 open roles · median 41 d
- Microchip Technology · 6 open roles · median 92 d
- Infineon Technologies · 4 open roles · median 37 d
How we counted: 102 open FPGA Design (RTL Design) roles from 26 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.