Senior Formal Verification Engineer - Santa Clara, CA, United States
$200,000 - $500,000 USD yearly
Originally posted 25 July 2026 by the employer.
Harden Velaura's Physical AI SoC using formal verification.
About the role
This role involves defining, owning, and scaling the formal verification effort for Velaura's Physical AI SoC.
What you'll do
- Own and drive formal verification for complex SoC blocks, including CPUs, control processors, floating-point units, vector/SIMD engines, and datapath-heavy designs.
- Write high-quality SVA properties and formal testbenches to prove functional correctness, including end-to-end and datapath-equivalence checks.
- Apply full proofs, bounded model checking, assume-guarantee reasoning, and abstraction to close proofs on deep-state designs.
- Debug counterexamples and drive convergence on hard proofs using abstraction, constraints, and decomposition.
- Verify floating-point and arithmetic units for IEEE-754 compliance using formal datapath and equivalence checking.
- Define constraints and modeling assumptions, and prove them consistent and non-over-constraining.
What you'll need
- 10+ years in functional verification, with substantial hands-on formal verification of complex digital systems.
- Track record solving hard formal problems—CPU/processor DV, floating-point/arithmetic datapath, or vector/SIMD units.
- Deep expertise with SystemVerilog Assertions (SVA) and formal property development.
- Hands-on experience with JasperGold, VC Formal, or Questa Formal / OneSpin.
- Understanding of floating-point arithmetic, IEEE-754, and datapath correctness.
- Strong scripting and automation skills for build, regression, and CI pipelines.
Nice to have
- Experience with formal datapath verification and arithmetic equivalence checking (e.g., C/C++/SystemC reference models vs. RTL).
- Experience verifying vector, SIMD, or matrix/tensor compute units.
- Experience with security verification (secure/non-secure isolation, information-flow, fault/side-channel) using formal methods.
- Experience with formal protocol verification of standard interconnects (e.g., AMBA AXI/ACE, CHI) using assertion IP.
- Familiarity with cache coherence, memory-consistency, and interconnect protocol verification.
- Familiarity with clock-domain-crossing (CDC) and reset-domain-crossing (RDC) formal signoff.
- Experience with sequential equivalence checking (SEC) and low-power (UPF) formal verification.
- Experience with AI, machine learning, or edge AI hardware.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Experience with functional-safety standards such as ISO 26262, IEC 61508, IEC 61511, or ISO 13849.
Skills: formal verification, SVA properties, bounded model checking, formal testbenches, IEEE-754 compliance
This role has been open 84 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1201 |
| Open roles in the wider Digital Design & Verification family | 26 | 3201 · 115 employers |
| Median days open | 32 d | 66 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: formal verification, SVA properties, bounded model checking, formal testbenches, IEEE-754 compliance
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.