Senior Engineer, PLL Design - San Jose, California, United States

Originally posted 5 October 2026 by the employer.

Design high-performance PLL and clock generation circuits for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies.

About the role

This role involves the design and development of high-performance PLL and clock generation circuits. You will focus on PLLs and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies.

What you'll do

• Design PLLs and clock generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications.
• Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators.
• Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink.
• Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation.
• Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets.
• Support bring-up, characterization, and debug of silicon prototypes in the lab.

What you'll need

• Master's with 2+ years of experience or PhD with 0 years of experience in a related field.
• Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm), including at least one of: integer-N, fractional-N, digital PLL, or sub-sampling PLL topologies.
• Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs.
• Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator.
• Strong Matlab/Simulink skills for behavioral modeling and system-level analysis.
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation.
• Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path).
• Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment.
• Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits, including frequency calibration, phase calibration, and background self-calibration logic.

Skills: PLL design, clock generation circuits, VCO/DCO, jitter budgeting, deep sub-micron CMOS