Senior Engineer, Physical Design AI/ML - San Jose, California, United States
$138,000 - $206,000 USD yearly
Originally posted 31 August 2026 by the employer.
Focus on applying AI/ML tools to improve design simulation accuracy and throughput in predicting design PPA.
About the role
This role involves applying AI/ML tools to improve design simulation accuracy and throughput in predicting design performance, power, and area (PPA).
What you'll do
- Design, build, and implement machine learning and generative models to optimize chip layout designs for performance, power, and area (PPA) efficiency, applying hardware design rules and constraints.
- Collaborate to automate all aspects of exploratory PDK generation, including developing automated Quality Assurance (QA) systems.
- Apply machine learning techniques to extract and develop correlations among data in different domains, such as device, RO benchmark circuits, and larger circuit blocks, at varying operating conditions.
- Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments for internal R&D teams.
What you'll need
- PhD with industry experience.
- RTL synthesis, place and route, and timing analysis skills.
- Understanding of clock and power delivery network schemes.
- Hands-on experience with machine learning or deep learning projects for scientific and engineering applications, including regression, surrogate modeling, inverse design, and graph neural networks.
- Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow.
- Experience in using Bayesian optimization and/or active learning frameworks for design space exploration.
- Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK).
Nice to have
- Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models.
- Proficiency in EDA tools for synthesis and layout.
- Prior experience using generative AI for chip design/optimization.
Skills: AI/ML tools, chip layout designs, PPA efficiency, PDK generation, machine learning
This role has been open 43 days — well below the 79-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
516
|
Median days open
79 d
|
Median salary
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (516 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 516 |
| Open roles in the wider Software, Firmware & Systems family | 13 | 6164 · 146 employers |
| Median days open | 26 d | 79 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: AI/ML tools, chip layout designs, PPA efficiency, PDK generation, machine learning
Who's hiring in this category
- Qualcomm · 104 open roles · median 105 d
- NVIDIA · 92 open roles · median 51 d
- AMD · 42 open roles · median 78 d
- Micron Technology · 27 open roles · median 68 d
- Mobileye · 20 open roles · median 72 d
- Analog Devices · 18 open roles · median 32 d
How we counted: 516 open AI/ML Hardware Engineering (AI ML Hardware) roles from 76 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.