Senior Engineer II - Physical Design - Canada - Burnaby, Canada
$86,000 - $186,000 USD yearly
Originally posted 17 September 2026 by the employer.
About the role
This role involves executing chip development methodologies as a key member of the Implementation team.
What you'll do
- Execute block level place and route and physical design verification.
- Develop macro level test structures and digital wrappers for analog cells.
- Perform synthesis and static timing for high-performance devices.
- Support customers through Microchip's Chip development flow.
- Collaborate with CAD, Packaging, Mixed Signal, Operations, and Design teams.
- Implement chip level, subsystem, CPU, and mixed signal blocks.
What you'll need
- 4-year degree in Electrical or Electronics Engineering with 7.5+ years of ASIC development experience.
- Design, Synthesis, Static Timing and Place & Route experience in high performance design.
- Hands-on experience in floorplanning, placement optimization, clock tree synthesis, and physical verification.
- Recent experience with full chip Physical Design activities.
- Understanding of Verilog and VHDL languages.
- Proficiency in Python/PERL/TCL scripting.
Nice to have
- Experience with 6nm process or lower.
Skills: block level place and route, physical design verification, floorplanning, placement optimization, clock tree synthesis
This role has been open 40 days — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 682 |
| Open roles in the wider Physical Implementation family | 28 | 1507 · 111 employers |
| Median days open | 80 d | 66 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: block level place and route, physical design verification, floorplanning, placement optimization, clock tree synthesis
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.