Senior Engineer - HBM Design for Test (DFT) - Richardson, TX, United States
Originally posted 6 August 2026 by the employer.
About the role
The Senior Engineer – HBM Design for Test (DFT) is responsible for the definition, implementation, integration, and support of DFT solutions across HBM core die and base die. This role focuses on driving defined DFT architectures and contributing to DFT specifications for HBM products.
What you'll do
- Implement and integrate DFT features for assigned HBM core die and base die designs in alignment with established DFT architecture
- Contribute to the development, review, and maintenance of DFT specifications, requirements, and implementation guidelines
- Ensure DFT implementations support high-quality, efficient, and manufacturable HBM products
- Translate manufacturing and test requirements into actionable DFT implementations
- Identify, debug, and resolve DFT-related issues during build execution, tape-out, and silicon bring-up
- Document DFT implementations, lessons learned, and procedures to support organizational knowledge exchange
What you'll need
- Bachelor’s degree in Electrical Engineering or related field
- 5+ years of experience in semiconductor development with exposure to DFT, design, verification, test, or silicon debug
- 1+ years of experience in memory architectures (HBM or DRAM preferred)
- 1+ years of experience implementing DFT features and supporting DFT-related debug and bring-up activities
Nice to have
- Experience working with DFT verification teams and coverage methodologies
- Familiarity with manufacturing test flows and test requirements for advanced memory products
- Analog/Digital design and verification experience in Cadence environments
This role has been open 73 days — well above the 58-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
58 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 242 |
| Open roles in the wider Digital Design & Verification family | 103 | 3201 · 115 employers |
| Median days open | 66 d | 58 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 39 open roles · median 44 d
- NVIDIA · 23 open roles · median 36 d
- Qualcomm · 23 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 66 d
- Synopsys · 14 open roles · median 25 d
- Micron Technology (this employer) · 10 open roles · median 65 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.