Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification) - Bengaluru, Karnataka, India
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves comprehensive CPU verification for RISC-V Vector, ALU, and FPU components, focusing on the execution pipeline and datapath behaviors. The position specifically supports RISC-V Vector, ALU, and FPU verification.
What you'll do
- Own verification planning and execution for Vector, ALU, floating-point blocks from testplanning to unit level verification and integration to core level.
- Drive verification strategy, test planning, Testbench development, tests writing, debug, coverage analysis, and closure for complex Vector, ALU, FPU execution-pipeline and datapath behaviours.
- Define effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.
- Develop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models.
- Partner with architecture, design, and verification teams to review specifications and identify risks.
- Contribute reusable methodology, automation, and infrastructure that improve verification quality and productivity.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
- Strong hands-on experience with SystemVerilog, UVM-based verification and modern verification methodologies.
- Solid understanding of computer architecture and CPU microarchitecture.
- Experience verifying one or more of the following areas: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
- Strong knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.
- Good scripting or programming skills in Python, C/C++, or similar languages used for DV infrastructure and automation.
Nice to have
- Experience with high-performance out-of-order CPU core verification.
- Experience developing high-value assertions, checkers, and scoreboards for control-heavy or dependency-sensitive CPU behavior.
- Experience applying formal verification to execution logic, control interactions, or datapath correctness.
- Experience collaborating effectively across architecture, design, performance, and verification teams.
Skills: CPU Verification, RISCV Vector, ALU, FPU Verification, test planning, Testbench development, SystemVerilog, UVM, coverage analysis
This role has been open 0 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1138
|
Median days open
57 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1138 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 52 | 1138 |
| Open roles in the wider Digital Design & Verification family | 83 | 3022 · 114 employers |
| Median days open | 45 d | 57 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: CPU Verification, RISCV Vector, ALU, FPU Verification, test planning, Testbench development, SystemVerilog, UVM, coverage analysis
Who's hiring in this category
- Qualcomm · 107 open roles · median 51 d
- AMD · 98 open roles · median 33 d
- NVIDIA · 90 open roles · median 66 d
- Micron Technology · 56 open roles · median 97 d
- Synopsys · 56 open roles · median 24 d
- SiFive (this employer) · 51 open roles · median 45 d
How we counted: 1138 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.