Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification) - Bengaluru, Karnataka, India
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This role involves comprehensive verification planning and execution for ALU and floating-point blocks, with a focus on formal and datapath verification. This position is central to the verification of complex CPU execution pipelines and datapath behaviors.
What you'll do
- Own verification planning and execution for ALU and floating-point blocks, focusing on formal and datapath verification.
- Drive verification strategy, test planning, debug, coverage analysis, and closure for complex Vector, ALU, FPU execution-pipeline, and datapath behaviors.
- Define effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.
- Develop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models.
- Partner with architecture, design, and verification teams to review specifications, identify risk, and improve verification completeness.
- Drive efficient root-cause debug across specification, RTL, tests, and verification infrastructure.
- Contribute reusable methodology, automation, and infrastructure for future CPU core programs.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
- Hands-on experience with SystemVerilog-based verification and modern verification methodologies.
- Understanding of computer architecture and CPU microarchitecture.
- Experience verifying one or more of: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
- Knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.
- Scripting or programming skills in Python, C/C++, or similar languages for DV infrastructure and automation.
Nice to have
- Experience with high-performance out-of-order CPU core verification.
- Experience developing high-value assertions, checkers, and scoreboards for control-heavy or dependency-sensitive CPU behavior.
- Experience applying formal verification to execution logic, control interactions, or datapath correctness.
- Experience collaborating effectively across architecture, design, performance, and verification teams.
Skills: ALU, floating-point blocks, formal verification, datapath verification, SystemVerilog-based verification, CPU microarchitecture
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1150
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1150 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 54 | 1150 |
| Open roles in the wider Digital Design & Verification family | 85 | 3066 · 114 employers |
| Median days open | 49 d | 60 d (−11 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: ALU, floating-point blocks, formal verification, datapath verification, SystemVerilog-based verification, CPU microarchitecture
Who's hiring in this category
- Qualcomm · 106 open roles · median 50 d
- AMD · 102 open roles · median 34 d
- NVIDIA · 89 open roles · median 68 d
- Synopsys · 62 open roles · median 17 d
- Micron Technology · 54 open roles · median 101 d
- SiFive (this employer) · 52 open roles · median 49 d
How we counted: 1150 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.