Senior Emulation Engineer - Santa Clara, CA, United States
$200,000 - $500,000 USD yearly
Originally posted 24 July 2026 by the employer.
Bring up and scale the emulation infrastructure for Velaura's Physical AI SoC.
About the role
As a Senior Emulation Engineer, you will bring up, own, and scale the emulation infrastructure for Velaura's Physical AI SoC.
What you'll do
- Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu. - Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues. - Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization. - Support HW/SW co-verification and pre-silicon software bring-up—firmware, drivers, runtime, and OS. - Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW. - Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
What you'll need
- 10+ years in hardware emulation and/or verification of complex digital systems. - Hands-on experience setting up emulation flows on Palladium, Veloce, or Zebu. - Ability to debug compile and elaboration issues on emulation platforms. - Proven ability to set up and optimize emulation regression flows for faster turnaround. - Strong grasp of computer, micro-, and SoC architecture and digital design fundamentals. - Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.
Nice to have
- Experience with design partitioning, capacity optimization, and multi-FPGA/multi-board emulation scaling. - Experience with FPGA prototyping and pre-silicon software bring-up environments. - Experience with HW/SW co-verification and system-level validation. - Familiarity with low-power methodologies and their verification/emulation criteria. - Experience with AI, machine learning, or edge AI hardware.
Skills: emulation flows, Palladium Veloce Zebu, HW/SW co-verification, regression flows, SystemVerilog UVM
This role has been open 84 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1201 |
| Open roles in the wider Digital Design & Verification family | 26 | 3201 · 115 employers |
| Median days open | 32 d | 66 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: emulation flows, Palladium Veloce Zebu, HW/SW co-verification, regression flows, SystemVerilog UVM
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.