Senior DRAM Systems Architecture - United States
$164,000 - $358,000 USD yearly
Originally posted 13 August 2026 by the employer.
Focus on DDR, LPDDR, HBM, and CXL-attached memory solutions.
About the role
You will focus on defining architectures for DDR, LPDDR, HBM, and CXL-attached memory, evaluating tradeoffs, and guiding technical decisions.
What you'll do
- Define architectures for DDR, LPDDR, HBM, CXL-attached memory, and emerging memory technologies.
- Develop analytical and simulation-based models to evaluate performance, reliability, power, thermal, and cost tradeoffs.
- Drive architecture requirements across DRAM, packaging, modules, controllers, platforms, and system software.
- Lead technical studies, roadmap development, and architecture recommendations supported by quantitative analysis.
- Influence cross-functional teams, mentor engineers, and contribute to patents, publications, and standards activities.
What you'll need
- Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, Applied Mathematics, Physics, or a related technical field.
- 8+ years of experience in memory systems, semiconductor architecture, computer architecture, or related technical areas.
- Strong knowledge of DRAM architecture, memory systems, or high-performance computing system architecture.
- Proven ability to develop architecture recommendations using quantitative analysis and engineering tradeoffs.
- Experience using AI-powered tools and methodologies, including Large Language Models, Agentic AI, Generative AI, or AI-enabled simulation environments.
Nice to have
- Experience working with DDR, LPDDR, HBM, CXL memory, MRDIMM/RDIMM, or emerging memory technologies.
- Experience with memory-system simulation or modeling tools such as Ramulator, Ramulator2, DRAMsim3, gem5, internal simulators, or equivalent platforms.
- Experience in queueing theory, stochastic modeling, performance modeling, reliability modeling, or mathematical optimization.
- Experience with RAS architecture, ECC, CRC, EDC, metadata, on-die ECC, rank-level protection, link protection, or system-wide robustness.
- Background in high-speed signaling, SI, clock distribution, packaging, module, PMIC, power, or thermal systems and experience participating in JEDEC or similar standards organizations.
Skills: DDR, LPDDR, HBM, CXL-attached memory, memory systems architecture
This role has been open 53 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DDR, LPDDR, HBM, CXL-attached memory, memory systems architecture
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.