Senior Director, Silicon Hardware Engineering - Boards, Packaging, & Reliability - San Jose, California, United States

Originally posted 11 September 2026 by the employer — open 9 days.

About the role

This role involves leading a global organization in chip package development, board hardware development, and silicon power and reliability engineering. The leader will define and execute technical strategy, development methodologies, and organizational capabilities to deliver high-performance, reliable silicon hardware solutions.

What you'll do

• Lead, develop, and scale chip package development, board hardware development, and silicon power and reliability engineering functions.
• Define and drive technical direction for advanced package technologies including 2.5D/3D IC, flip-chip, and high-density interconnect.
• Oversee board-level hardware development from concept through bring-up, ensuring design-for-manufacturability and design-for-test.
• Lead silicon power and reliability programs including power budgeting, electromigration, ESD, and reliability qualification.
• Drive disciplined technical reviews and engineering decision-making across package, board, SI/PI, power, and reliability activities.
• Manage complex, multi-vendor relationships with OSATs, PCB fabricators, substrate suppliers, and EDA vendors.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or closely related field.
• 15+ years of progressive experience in semiconductor hardware engineering, with at least 5 years in a senior leadership or director-level role.
• Demonstrated experience managing global, cross-functional engineering teams across U.S. and Asian sites.
• Deep technical expertise in chip package development, including advanced packaging, substrate design, and OSAT management.
• Proven experience in chip board hardware development, including schematic design, PCB layout, and bring-up.
• Strong hands-on background in signal integrity and power integrity analysis and methodologies, including experience with industry-standard tools such as Ansys SIwave, Cadence Sigrity, HyperLynx, or equivalent.
• Solid understanding of silicon design development methodologies, including synthesis, place and route (P&R), timing closure, and DFT.
• Track record of delivering measurable cost-reduction programs across package and board hardware.
• Experience managing and qualifying multiple external vendors and OSATs simultaneously.

Skills: chip package development, advanced package technologies, 2.5D/3D IC, OSAT management, reliability qualification