Senior Director, Silicon Architecture and Design Engineering (Ethernet) - San Jose, California, United States
$231,500 - $341,075 USD yearly
Originally posted 23 September 2026 by the employer.
This role focuses on multi-generation Ethernet roadmap across Altera’s programmable device portfolio.
About the role
This role leads Altera's Ethernet Center of Excellence, owning the technical direction, architecture, methodologies, and multi-generation Ethernet roadmap. The position focuses on Ethernet across Altera’s programmable device portfolio, including FPGA, SoC, and platform technologies.
What you'll do
- Lead a silicon engineering organization delivering FPGA, ASIC, and SoC products.
- Own end-to-end silicon execution from product definition to microarchitecture, managing RTL, verification, DFT, emulation, implementation, bring-up, and validation.
- Define and drive Ethernet architecture including MAC, PCS, FEC, Auto-Negotiation, Link Training, and high-speed PHY/SerDes integration.
- Represent Altera externally with customers, partners, and standards bodies (IEEE 802.3, Ultra Ethernet Consortium, OIF).
- Provide technical leadership for networking datapath architecture, including packet processing, L2/L3 forwarding, QoS, traffic management, and buffering.
- Drive large, complex silicon programs: planning, resource alignment, milestone tracking, and risk management.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
- 15+ years in silicon engineering, ASIC, SoC, or FPGA product development.
- 10+ years in networking and Ethernet technologies, including architecture, silicon development, or product development.
- Deep expertise in IEEE 802.3 Ethernet architecture, from MAC/PCS through high-speed PHY/SerDes integration.
- Experience with multiple generations of high-speed Ethernet through 800G-class, plus AI/data center scale-out networking (RDMA/RoCE, lossless Ethernet, congestion control, or Ultra Ethernet).
- 10+ years leading or working across the silicon development lifecycle, from architecture and RTL through verification, DFT, emulation, physical design, post-silicon validation, and production.
Nice to have
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience leading silicon development at advanced process nodes.
- Experience with emerging 1.6T Ethernet and 112G/224G-class SerDes.
- Experience with FPGA or heterogeneous SoC platforms, including Ethernet IP, transceiver integration, and third-party PHY/controller IP.
Skills: Ethernet architecture, MAC/PCS, high-speed PHY/SerDes, FPGA, SoC
This role has been open 17 days — well below the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
455
|
Median days open
78 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (455 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 455 |
| Open roles in the wider Digital Design & Verification family | 23 | 3166 · 114 employers |
| Median days open | 17 d | 78 d (−61 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: Ethernet architecture, MAC/PCS, high-speed PHY/SerDes, FPGA, SoC
Who's hiring in this category
- Qualcomm · 74 open roles · median 82 d
- NVIDIA · 58 open roles · median 65 d
- AMD · 34 open roles · median 60 d
- Apple · 34 open roles · median 5 d
- Arm Holdings · 27 open roles · median 108 d
- NXP Semiconductors · 21 open roles · median 110 d
How we counted: 455 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.