Senior Director R&D Engineering (Interface PHY / Ethernet SerDes)
Originally posted 23 July 2026 by the employer.
This role focuses on building 112G and 224G Ethernet SerDes IP.
About the role
This role leads an R&D organization developing Interface PHY and Ethernet SerDes IP. You will lead the team building 112G and 224G Ethernet SerDes IP that powers AI infrastructure and hyperscale data centers.
What you'll do
- Lead an R&D organization developing 112G/224G Ethernet SerDes and Interface PHY IP for AI/HPC, networking, and data center markets.
- Own execution planning, staffing, and delivery commitments across multiple concurrent programs and customer milestones.
- Drive technical alignment across architecture, analog, digital, verification, firmware, and customer support teams.
- Partner with product and program management to translate roadmap priorities into executable engineering plans.
- Define processes for milestone reviews, risk management, and decision-making that keep programs moving.
- Lead resolution of customer-critical issues from triage through root-cause analysis and corrective action.
- Develop engineering talent through coaching, performance management, hiring, and succession planning.
What you'll need
- BS/MS/PhD in Electrical Engineering, Computer Engineering, or related discipline.
- 15+ years of semiconductor development experience with progression into engineering leadership.
- Proven experience leading engineering teams with significant schedule, quality, and customer impact.
- Strong understanding of SerDes PHY digital development flows including architecture, RTL, verification, firmware, integration, and release.
- Experience with Ethernet, PCIe/CXL, or other high-speed protocols.
- Track record managing execution across distributed teams and multiple stakeholders.
Skills: SerDes IP, 112G/224G Ethernet, Interface PHY, AI/HPC, distributed teams
This role has been open 67 days — below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 38 | 1385 · 108 employers |
| Median days open | 32 d | 76 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes IP, 112G/224G Ethernet, Interface PHY, AI/HPC, distributed teams
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys (this employer) · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.