Senior Director, Central Engineering – SoC Design & Modeling Methodologies - San Jose, United States
Originally posted 27 October 2026 by the employer.
About the role
This position serves as the leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture across multiple product lines.
What you'll do
- Define and drive the strategic roadmap for workload analysis and performance for both IPs and products across the company. - Lead architecture performance reviews and technical direction for complex IP/SoC and subsystem developments. - Establish best practices for hardware/software co-design, virtual platforms, executable specifications, and model-based development. - Define and analyze AI workloads and characterize the system performance required for them. - Provide technical leadership across cross-functional teams spanning architecture, design, verification, emulation, and software. - Build, lead, and mentor high-performing engineering teams, including directors, principal engineers, and distinguished engineers.
What you'll need
- MS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. - 15+ years of experience in semiconductor or SoC development, with 8+ years of technical leadership experience. - Proven experience leading performance and workload analysis, HW/SW co-optimization, and SoC architecture. - Hands-on experience with performance and workload benchmarking, SoC performance modeling, virtual platforms, and executable specifications. - Deep technical understanding of digital design methodologies, SoC verification methodologies, design and verification automation flows, and IP/subsystem development.
Skills: SoC architecture, workload analysis, HW/SW co-design, performance modeling, AI workloads
This role has been open 0 days — well below the 81-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
486
|
Median days open
81 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (486 roles · 68 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 486 |
| Open roles in the wider Digital Design & Verification family | 82 | 3359 · 116 employers |
| Median days open | 81 d | 81 d (same as this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: SoC architecture, workload analysis, HW/SW co-design, performance modeling, AI workloads
Who's hiring in this category
- Qualcomm · 83 open roles · median 81 d
- NVIDIA · 54 open roles · median 69 d
- Apple · 44 open roles · median 18 d
- AMD · 36 open roles · median 76 d
- Arm Holdings · 27 open roles · median 124 d
- Micron Technology · 21 open roles · median 103 d
How we counted: 486 open SoC/Chip Architecture (SOC Architecture) roles from 68 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.