Senior Director, AMS Layout Engineering

Originally posted 22 October 2026 by the employer.

About the role

As Senior Director of AMS Layout Engineering, you will lead the physical implementation of advanced high-speed analog and mixed-signal circuits for SerDes technologies.

What you'll do

• Lead AMS layout engineering for advanced high-speed SerDes PHYs, driving physical implementation, optimization, and sign-off across critical analog and mixed-signal circuit blocks.
• Drive layout solutions at advanced nodes, addressing complex design rules, restrictive patterning requirements, parasitic effects, device matching, signal integrity, power integrity, and electromigration.
• Partner with circuit designers to optimize layout-sensitive performance, including bandwidth, jitter, noise, matching, power consumption, and overall silicon robustness at 100G+ per-lane data rates.
• Establish and improve layout methodologies, design guidelines, verification flows, and quality standards to enable predictable execution and first-silicon success.
• Collaborate with AMS design, digital implementation, technology, package, and silicon validation teams to resolve complex integration challenges.
• Build and scale an AMS layout organization through hiring, technical mentorship, talent development, project planning, and resource allocation across multiple concurrent development efforts.

What you'll need

• BS, MS, or PhD in Electrical Engineering, Microelectronics, or a related field.
• Proven experience delivering advanced-node analog or mixed-signal designs at 5nm or below.
• Strong understanding of layout techniques for high-speed SerDes and PHY circuits, including high-speed transmitters, receivers, clocking circuits, PLLs, DLLs, and timing-critical analog blocks.
• Demonstrated understanding of advanced process design rules, parasitic extraction, physical verification, device matching, signal integrity, and power integrity.
• Experience leading silicon development programs from early floorplanning and layout planning through physical verification, tape-out, and silicon bring-up.
• Proven ability to recruit, develop, mentor, and retain engineering talent.

Nice to have

• Direct experience developing and delivering 100G+ per-lane SerDes PHYs.
• Experience leading AMS layout teams for high-speed connectivity products targeting AI accelerators, high-performance computing, networking, or advanced data center applications.
• Deep expertise in layout-sensitive circuit optimization, including parasitic management, coupling and crosstalk mitigation, clock distribution, supply integrity, and electromagnetic interactions.
• Experience with advanced packaging, chiplet integration, and high-bandwidth die-to-die interfaces.
• A track record of establishing scalable engineering methodologies and delivering silicon across multiple technology generations.
• Experience building engineering teams in a high-growth semiconductor organization.

Skills: AMS layout, analog layout, IC layout, custom layout

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