Senior Digital Verification Engineer - Contract
$80 - $130 USD yearly
Originally posted 14 October 2026 by the employer.
Join our newly formed Verification & Emulation team to take ownership of verification for complex blocks and subsystems in our SoC, including Efficient's proprietary Fabric technology.
About the role
This role involves owning verification for complex blocks and subsystems within the company's SoC, specifically including Efficient Computer's proprietary Fabric technology.
What you'll do
- Own verification of assigned blocks and subsystems from specification review through coverage sign-off.
- Architect, build, or extend UVM/SystemVerilog testbenches, including agents, scoreboards, reference models, sequences, and constrained-random tests.
- Write SystemVerilog assertions and functional coverage models, driving functional and code coverage to closure.
- Debug complex simulation failures and collaborate with RTL designers to root-cause and fix bugs.
- Report verification status, risks, and coverage gaps to the DV lead and design team.
- Document verification environments for handover and maintenance by the full-time team.
What you'll need
- 8+ years of ASIC/SoC design verification experience, with multiple projects from testbench development through tapeout.
- Expert-level proficiency in UVM testbench architecture and SystemVerilog for verification, including classes, constraints, interfaces, functional coverage, and assertions (SVA).
- Demonstrated ability to drive functional and code coverage to sign-off on multi-million-gate designs.
- Strong capability to debug complex simulation failures independently using industry-standard tools (VCS/Verdi, Xcelium, or Questa).
- Proficiency in Python for regression automation, log analysis, and coverage post-processing.
- Ability to ramp quickly on new designs and deliver with minimal supervision.
Skills: Digital Verification, UVM, SystemVerilog, testbenches, coverage closure, simulation failures
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1187 |
| Open roles in the wider Digital Design & Verification family | 6 | 3192 · 115 employers |
| Median days open | 43 d | 64 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Digital Verification, UVM, SystemVerilog, testbenches, coverage closure, simulation failures
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.