Senior Digital Design Verification Engineer - Austin, United States
Originally posted 15 September 2026 by the employer. Relisted by the employer on 22 October 2026.
power management SoCs
About the role
Renesas is seeking a Senior Digital Design Verification Engineer to own verification of complex digital blocks and major features for power management SoCs from planning through closure. The role focuses on power management SoCs integrating digital control, telemetry, fault management, communication interfaces, configurable peripherals, and power-control functions.
What you'll do
- Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure. - Develop feature-based verification plans from product, architecture, and microarchitecture specifications, identifying corner cases and risks. - Build and extend reusable SystemVerilog and UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models. - Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions. - Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data. - Debug RTL, testbench, assertion, integration, and regression failures in collaboration with design and firmware teams.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - 4 or more years of relevant digital design verification experience. - Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure. - Proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions. - Hands-on experience developing and debugging reusable UVM environments, test plans, checkers, scoreboards, and coverage models. - Working knowledge of digital design fundamentals, including state machines, clocks and resets, interrupts, register interfaces, memories, and clock-domain crossings. - Proficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl.
Nice to have
- Experience verifying complex SoCs, power management ICs, voltage regulators, digital controllers, or mixed-signal products. - Experience verifying RTL interfaces to embedded processors, memory-mapped peripherals, and firmware-controlled hardware features. - Familiarity with PMBus, AVSBus, SVID or SVI3, I2C, SPI, or similar control and communication protocols. - Understanding of telemetry, fault and alert handling, power sequencing, multiphase regulation, or digital control loops. - Experience with Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi, or comparable tools. - Experience with formal verification, gate-level simulation, silicon bring-up, or pre-silicon-to-silicon correlation.
This role has been open 37 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 1070 |
| Open roles in the wider Digital Design & Verification family | 82 | 3298 · 115 employers |
| Median days open | 59 d | 62 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.