Originally posted 21 September 2026 by the employer — open 0 days.
Join a team creating high impact micro-controllers (MCU) at the edge.
About the role
This role involves leading and executing the full digital IC design flow for complex System-on-Chip (SOC). The focus is on high impact micro-controllers (MCU) as part of intelligent AI at the Edge.
What you'll do
- Lead and execute the full digital IC design flow for complex System-on-Chip (SOC), including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), formal verification, and power analysis.
- Contribute to design for testability (DFT) implementation and verification.
- Collaborate with analog, mixed-signal, and software teams to define interfaces, optimize system performance, and ensure seamless integration.
- Develop and implement innovative digital architectures and design methodologies to meet challenging performance, power, and area targets.
- Perform comprehensive design verification using simulation tools, formal verification techniques, and hardware emulation.
- Participate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
- Mentor junior engineers, provide technical guidance, and contribute to continuous improvement of design processes and methodologies.
What you'll need
- Master's degree in Electrical Engineering, Electronics Engineering, or related field.
- Minimum of 5+ years of experience in digital IC design.
- Expertise in Verilog/SystemVerilog for RTL design and verification.
- Proven experience with industry-standard EDA tools for synthesis, STA (e.g., Synopsys Design Compiler, Cadence Genus, Primetime), formal verification (e.g., Synopsys Formality), and simulation (e.g., VCS, QuestaSim).
- Strong understanding of digital design principles, clock domain crossing (CDC) issues, power integrity, and low-power design techniques.
- Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and design flow optimization.
- Familiarity with mixed-signal integration challenges and verification methodologies.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
938
|
Median days open
62 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (938 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 53 | 938 |
| Open roles in the wider Digital Design & Verification family | 146 | 3020 · 114 employers |
| Median days open | 67 d | 62 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Qualcomm · 143 open roles · median 54 d
- AMD · 61 open roles · median 62 d
- Synopsys · 57 open roles · median 30 d
- NXP Semiconductors (this employer) · 51 open roles · median 68 d
- NVIDIA · 48 open roles · median 45 d
- Analog Devices · 39 open roles · median 74 d
How we counted: 938 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.