Senior Digital/AMS Validation and Integration Engineer - San Jose (Holger Way), United States
$166,200 - $228,500 USD yearly
Originally posted 13 March 2026 by the employer.
About the role
As a Senior Digital/AMS Validation and Integration Engineer, you will drive the integration of digital logic into Automotive SerDes transceivers. You will own the RTL design of the Digital-Analog Wrapper, manage the path through timing closure, and support lab validation.
What you'll do
- Develop and integrate Verilog and SystemVerilog RTL for control loops, calibration engines, and high-speed data paths in 10G+ transceivers. - Define and implement the digital interface for analog blocks, including ADCs, PLLs, and driver stages, ensuring signal crossing between asynchronous domains. - Lead the digital implementation flow and collaborate with physical design engineers to achieve timing closure across high-speed clock domains. - Bring up silicon in the lab, using Python-based tools to exercise RTL features, debug state machines, and verify control and status registers (CSRs). - Run block-level and chip-level simulations to ensure digital control logic handles analog PVT variations and startup sequences.
What you'll need
- BSEE or MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration. - Proficiency in SystemVerilog and Verilog for synthesis. - Solid understanding of Static Timing Analysis (STA), clock domain crossing (CDC), and Synopsys Design Constraints (SDC). - Experience with Python or Perl for hardware control, test automation, and data processing. - Hands-on lab experience using logic analyzers, high-speed scopes, and JTAG, I2C, or SPI protocols for on-chip debugging.
Nice to have
- Experience with 10GBase-T, ASA, or Automotive Ethernet standards. - Familiarity with the hand-off between digital logic and high-speed Analog Front Ends (AFE). - Knowledge of DFT and BIST insertion for high-speed links. - Ability to create Verilog-A models.
Skills: RTL design of the Digital-Analog Wrapper, control loops, calibration engines, high-speed data paths in 10G transceivers, digital interface for analog blocks (ADCs, PLLs), Silicon Validation
This role has been open 222 days — well above the 104-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
150
|
Median days open
104 d
|
Median salary
$180k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (150 roles · 39 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 150 |
| Open roles in the wider Analog & Mixed-Signal family | 54 | 1453 · 106 employers |
| Median days open | 38 d | 104 d (−66 d vs this employer) |
| Median salary (USD postings) | — | $180k |
Skills observed across this category: RTL design of the Digital-Analog Wrapper, control loops, calibration engines, high-speed data paths in 10G transceivers, digital interface for analog blocks (ADCs, PLLs), Silicon Validation
Who's hiring in this category
- Analog Devices · 16 open roles · median 86 d
- SiTime · 11 open roles · median 216 d
- Infineon Technologies · 10 open roles · median 76 d
- Apple · 9 open roles · median 12 d
- Microchip Technology · 8 open roles · median 215 d
- NVIDIA · 8 open roles · median 41 d
How we counted: 150 open Mixed-Signal Design (Mixed Signal) roles from 39 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.