Senior DFT Power Methodology Engineer - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 13 July 2026 by the employer.
About the role
The Senior DFT Power Methodology Engineer develops methodologies across DFT power, thermal, and voltage noise domains. The role focuses on low-power and thermal solutions for manufacturing tests on datacenter GPUs.
What you'll do
- Develop low-power and thermal solutions for manufacturing tests applied to datacenter GPUs. - Partner with Product Development and Power Architecture teams to implement methodologies aimed at improving outgoing chip quality. - Execute post-silicon data analysis for power to architect future solutions. - Develop and deploy DFT methodologies using Applied ML and Gen AI solutions. - Mentor junior engineers on test designs and trade-offs, including cost and quality metrics.
What you'll need
- BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power. - Understanding of fundamental DFT topics and VLSI areas of power, timing, and voltage noise. - Knowledge in using statistical tools for data analysis and insights. - Exposure to multi-functional areas including RTL & clocks design, STA, place-n-route, and power. - Experience in silicon debug and bring-up on ATE or SLT platforms. - Programming ability applicable to AI coding harnesses.
Nice to have
- Experience in Power Analysis, Thermal Analysis & IR Drop tools. - Experience in application of AI for EDA-related problem-solving. - Experience in managing DFT Power Methodology for designs. - Experience in post-silicon debug for thermal & IR Drop.
Skills: DFT Power, Thermal & Voltage Noise Methodology, low power solutions, manufacturing tests, Applied ML & Gen AI
This role has been open 98 days — well above the 60-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
246
|
Median days open
60 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (246 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 246 |
| Open roles in the wider Digital Design & Verification family | 229 | 3244 · 116 employers |
| Median days open | 30 d | 60 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: DFT Power, Thermal & Voltage Noise Methodology, low power solutions, manufacturing tests, Applied ML & Gen AI
Who's hiring in this category
- AMD · 40 open roles · median 40 d
- NVIDIA (this employer) · 24 open roles · median 29 d
- Qualcomm · 23 open roles · median 103 d
- NXP Semiconductors · 19 open roles · median 43 d
- Synopsys · 14 open roles · median 27 d
- Micron Technology · 10 open roles · median 67 d
How we counted: 246 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.